Top Gate Electrode Research Articles

Amorphous In–Ga–Zn–O Dual-Gate TFTs: Current–Voltage Characteristics and Electrical Stress Instabilities

We studied the electrical characteristics and electrical stress instabilities of amorphous In-Ga-Zn-O (-IGZO) dual-gate thin-film-transistors (DG TFTs). A threshold voltage of the bottom-gate (BG)-driven -IGZO DG TFTs showed a linear dependence on the top-gate (TG) voltage. The slope of this dependence is associated with the ratio of the TG to BG insulator capacitance. The BG-driven DG TFT showed linear field-effect mobility comparable to that of a single-gate (SG) TFT without the TG electrode and a smaller saturation field-effect mobility and a larger subthreshold swing in comparison to the SG TFT. These characteristics were explained by the BG-driven DG TFT model formulated by taking the TG bias effect into account. The TG interface showed worse stability under an electric bias stress in comparison to the BG interface. It was also found that a negative voltage applied to the TG improved the stability of the DG TFT under a constant-current stress. These observations suggest that the BG-driven -IGZO DG TFTs with the appropriate negative TG voltage applied can simultaneously show both normally off characteristics and higher stability than the SG TFTs.

A spiking neuron circuit based on a carbon nanotube transistor

A spiking neuron circuit based on a carbon nanotube (CNT) transistor is presented in this paper. The spiking neuron circuit has a crossbar architecture in which the transistor gates are connected to its row electrodes and the transistor sources are connected to its column electrodes. An electrochemical cell is incorporated in the gate of the transistor by sandwiching a hydrogen-doped poly(ethylene glycol)methyl ether (PEG) electrolyte between the CNT channel and the top gate electrode. An input spike applied to the gate triggers a dynamic drift of the hydrogen ions in the PEG electrolyte, resulting in a post-synaptic current (PSC) through the CNT channel. Spikes input into the rows trigger PSCs through multiple CNT transistors, and PSCs cumulate in the columns and integrate into a ‘soma’ circuit to trigger output spikes based on an integrate-and-fire mechanism. The spiking neuron circuit can potentially emulate biological neuron networks and their intelligent functions.

Gate tunable non-linear currents in bilayer graphene diodes

Electric transport of double gated bilayer graphene devices is studied as a function of charge density and bandgap. A top gate electrode can be used to control locally the Fermi level to create a pn junction between the double-gated and single-gated region. These bilayer graphene pn diodes are characterized by non-linear currents and directional current rectification, and we show the rectified direction of the source-drain voltage can be controlled by using gate voltages. A systematic study of the pn junction characteristics allows to extract a gate-dependent bandgap value which ranges from 0 meV to 130 meV.

Structure and electrical properties of sputtered TiO2/ZrO2 bilayer composite dielectrics upon annealing in nitrogen

The high-k dielectric TiO2/ZrO2 bilayer composite film was prepared on a Si substrate by radio frequency magnetron sputtering and post annealing in N2 at various temperatures in the range of 573 K to 973 K. Transmission electron microscopy observation revealed that the bilayer film fully mixed together and had good interfacial property at 773 K. Metal-oxide-semiconductor capacitors with high-k gate dielectric TiO2/ZrO2/p-Si were fabricated using Pt as the top gate electrode and as the bottom side electrode. The largest property permittivity of 46.1 and a very low leakage current density of 3.35 × 10-5 A/cm2 were achieved for the sample of TiO2/ZrO2/Si after annealing at 773 K.

Electric-field control of magnetic domain-wall velocity in ultrathin cobalt with perpendicular magnetization

Controlling the displacement of a magnetic domain wall is potentially useful for information processing in magnetic non-volatile memories and logic devices. A magnetic domain wall can be moved by applying an external magnetic field and/or electric current, and its velocity depends on their magnitudes. Here we show that the applying an electric field can change the velocity of a magnetic domain wall significantly. A field-effect device, consisting of a top-gate electrode, a dielectric insulator layer, and a wire-shaped ferromagnetic Co/Pt thin layer with perpendicular anisotropy, was used to observe it in a finite magnetic field. We found that the application of the electric fields in the range of ± 2-3 MV cm(-1) can change the magnetic domain wall velocity in its creep regime (10(6)-10(3) m s(-1)) by more than an order of magnitude. This significant change is due to electrical modulation of the energy barrier for the magnetic domain wall motion.

Electrical Properties and Stability of Dual-Gate Coplanar Homojunction DC Sputtered Amorphous Indium–Gallium–Zinc–Oxide Thin-Film Transistors and Its Application to AM-OLEDs

The electrical characteristics and stability of dual-gate (DG) coplanar homojunction amorphous indium-gallium-zinc-oxide thin-film transistors (a-IGZO TFTs) on glass substrates are described herein. In this device structure, both top gate (TG) and bottom gate are defined by lithography, allowing independent biasing when adjacent TFTs are present. The DG a-IGZO TFT demonstrates excellent electrical performance with subthreshold swing (SS) of 99 mV/dec, field-effect mobility of 15.1 , and on- off current ratio of . By applying various bias voltages on the TG electrode, it is found that the TFT threshold voltage can be controlled without any change of the SS and off current. Under conditions of negative bias temperature stress (BTS), the transfer curves of the TFT exhibit negligible shifts after 10 000 s. Larger shifts are observed under conditions of a positive BTS. Finally, the application of this DG device to active-matrix organic light-emitting displays is suggested.

Air stable complementary polymer circuits fabricated in ambient condition by inkjet printing

Air stable complementary polymer inverters were demonstrated by inkjet printing of both top-gate electrodes and the semiconductors in ambient conditions. The p-type and n-type polymer semiconductors were also thermally annealed in ambient conditions after printing. The good performance of circuits in ambient condition shows that the transistors are not only air-stable in term of ambient humidity and oxygen, but also inert to ion migration through dielectrics from the printed gate. The result obtained here has further confirmed the feasibility of fabrication of low-cost polymer complementary circuits in a practical environment.

Top-Gate ZnO Nanowire Transistors and Integrated Circuits with Ultrathin Self-Assembled Monolayer Gate Dielectric

A novel approach for the fabrication of transistors and circuits based on individual single-crystalline ZnO nanowires synthesized by a low-temperature hydrothermal method is reported. The gate dielectric of these transistors is a self-assembled monolayer that has a thickness of 2 nm and efficiently isolates the ZnO nanowire from the top-gate electrodes. Inverters fabricated on a single ZnO nanowire operate with frequencies up to 1 MHz. Compared with metal-semiconductor field-effect transistors, in which the isolation of the gate electrode from the carrier channel relies solely on the depletion layer in the semiconductor, the self-assembled monolayer dielectric leads to a reduction of the gate current by more than 3 orders of magnitude.

ZnO nanowire transistor inverter using top-gate electrodes with different work functions

ZnO-nanowire field effect transistors (FETs) with a top gate Al2O3 dielectric and different metal electrodes were fabricated to form a low voltage electrical inverter. Two FETs with Pd and Ni/Ti gates whose respective work functions are so different as 5.3 and 4.3 eV were chosen to play as driver and load, since such different work functions lead to a threshold voltage (VT) difference of at least 1 V between the two FETs. Our FETs with Pd and Ni/Ti, respectively, showed 0.8 and −0.3 V for their VT values, while our inverter exhibited a desirable voltage transfer characteristics with voltage gain of over 15 during low voltage electrical gating.

Interfacial Reaction and Electrical Properties of HfO2 Film Gate Dielectric Prepared by Pulsed Laser Deposition in Nitrogen: Role of Rapid Thermal Annealing and Gate Electrode

The high-k dielectric HfO(2) thin films were deposited by pulsed laser deposition in nitrogen atmosphere. Rapid thermal annealing effect on film surface roughness, structure and electrical properties of HfO(2) film was investigated. The mechanism of interfacial reaction and the annealing atmosphere effect on the interfacial layer thickness were discussed. The sample annealed in nitrogen shows an amorphous dominated structure and the lowest leakage current density. Capacitors with high-k HfO(2) film as gate dielectric were fabricated, using Pt, Au, and Ti as the top gate electrode whereas Pt constitutes the bottom side electrode. At the gate injection case, the Pt- and Au-gated metal oxide semiconductor devices present a lower leakage current than that of the Ti-gated device, as well as similar leakage current conduction mechanism and interfacial properties at the metal/HfO(2) interface, because of their close work function and chemical properties.

Electroluminescence with micro-watt output from ultra-small sized Si quantum dots/amorphous SiO 2 multilayers prepared by laser crystallization method

We report the fabrication of Si quantum dots (QDs)/SiO 2 multilayers by using KrF excimer laser (248 nm) crystallization of amorphous Si/SiO 2 multilayered structures on ITO coated glass substrates. Raman spectra and transmission electron microscopy demonstrate the formation of Si QDs and the size can be controlled as small as 1.8 nm. After laser crystallization, Al electrode is evaporated to obtain light emitting devices and the room temperature electroluminescence (EL) can be detected with applying the DC voltage above 8 V on the top gate electrode. The luminescent intensity increases with increasing the applied voltage and the micro-watt light output is achieved. The EL behaviors for samples with different Si dot sizes are studied and it is found that the corresponding external quantum efficiency is significantly enhanced in sample with ultra-small sized Si QDs.

Nanoparticle single-electron transistor with metal-bridged top-gate and nanogap electrodes

Au nanoparticle single-electron transistors with metal-bridged top-gates and nanogap electrodes were fabricated using two consecutive electron beam lithography and electroless Au plating steps. The metal-bridged top-gate electrodes were suspended above electroless Au plated nanogap electrodes. Au nanoparticles (5.2 nm in diameter) were chemisorbed between the nanogap electrodes after top-gate fabrication. Clear Coulomb diamonds were observed at 9 K. The gate capacitance Cg of the top-gate electrodes was 99 zF, which is 10 times larger than that of a similar device with only side-gate electrodes.

CMOS-compatible fabrication of top-gated field-effect transistor silicon nanowire-based biosensors

Field-effect transistor (FET) nanowire-based biosensors are very promising tools for medical diagnosis. In this paper, we introduce a simple method to fabricate FET silicon nanowires using only standard microelectromechanical system (MEMS) processes. The key steps of our fabrication process were a local oxidation of silicon (LOCOS) and anisotropic KOH etchings that enabled us to reduce the width of the initial silicon structures from 10 µm to 170 nm. To turn the nanowires into a FET, a top-gate electrode was patterned in gold next to them in order to apply the gate voltage directly through the investigated liquid environment. An electrical characterization demonstrated the p-type behaviour of the nanowires. Preliminary chemical sensing tested the sensitivity to pH of our device. The effect of the binding of streptavidin on biotinylated nanowires was monitored in order to evaluate their biosensing ability. In this way, streptavidin was detected down to a 100 ng mL−1 concentration in phosphate buffered saline by applying a gate voltage less than 1.2 V. The use of a top-gate electrode enabled the detection of biological species with only very low voltages that were compatible with future handheld-requiring applications. We thus demonstrated the potential of our devices and their fabrication as a solution for the mass production of efficient and reliable FET nanowire-based biological sensors.

Electro-oxidized Epitaxial Graphene Channel Field-Effect Transistors with Single-Walled Carbon Nanotube Thin Film Gate Electrode

We report the effect of electrochemical oxidation in nitric acid on the electronic properties of epitaxial graphene (EG) grown on silicon carbide substrates; we demonstrate the availability of an additional reaction channel in EG, which is not present in graphite but which facilitates the introduction of the reaction medium into the graphene galleries during electro-oxidation. The device performance of the chemically processed graphene was studied by patterning the EG wafers with two geometrically identical macroscopic channels; the electro-oxidized channel showed a logarithmic increase of resistance with decreasing temperature, which is ascribed to the scattering of charge carriers in a two-dimensional electronic gas, rather than the presence of an energy gap at the Fermi level. Field-effect transistors were fabricated on the electro-oxidized and pristine graphene channels using single-walled carbon nanotube thin film top gate electrodes, thereby allowing the study of the effect of oxidative chemistry on the transistor performance of EG. The electro-oxidized channel showed higher values for the on-off ratio and the mobility of the graphene field-effect transistor, which we ascribe to the availability of high-quality internal graphene layers after electro-oxidation of the more defective top layers. Thus, the present oxidative process provides a clear contrast with previously demonstrated covalent chemistry in which sp(3) hybridized carbon atoms are introduced into the graphitic transport layer of the lattice by carbon-carbon bond formation, thereby opening an energy gap.

Large Signal Operation of Small Band-Gap Carbon Nanotube-Based Ambipolar Transistor: A High-Performance Frequency Doubler

A small band-gap carbon nanotube (SBG CNT) with a large diameter of 4 nm has been used to fabricate ambipolar field-effect transistors (FETs) with ultrahigh carrier mobility of more than 18 300 and 8300 cm(2)/V x s for holes and electrons, respectively. Using a top-gate device geometry with 12 nm HfO(2) being the gate oxide, the SBG CNT-based FET exhibits an almost perfect symmetric ambipolar transfer characteristic without any noticeable hysteresis, and a highly efficient frequency doubler is constructed based on this near perfect ambipolar FET. The SBG CNT-based frequency doubler is shown to be able to operate in a large signal mode where the input AC signal, being applied to the top-gate electrode, drives the FET operating alternatively in a p- or n-region yielding an output signal at the drain electrode with doubled frequency and high conversion efficiency. For an input AC signal of 1 kHz, detailed frequency power spectrum analysis shows that more than 95% of the output signal is concentrated at the doubled frequency at 2 kHz, with a gain of more than 0.15, and this represents the highest gain so far achieved in carbon-based devices, including graphene-based devices.

Improved gate-control in InAs nanowire structures by the use of GdScO3 as a gate dielectric

We investigated the properties of gadolinium scandate (GdScO3) as a gate dielectric for top-gate electrodes on undoped InAs nanowires. It is demonstrated that due to the high dielectric constant of GdScO3 (k=22), a better control of the conductance of the nanowire is achieved compared to a reference SiO2-isolated back-gate electrode. We analyzed the output and transfer characteristics of top-gate-controlled InAs wires at room temperature and at temperatures down to 4 K. Owing to the good coverage of the InAs nanowire by the 50-nm-thick GdScO3 layer, which was deposited by pulsed-laser deposition, the gate leakage current is sufficiently suppressed.

Vertical electric field tuning of the exciton fine structure splitting and photon correlation measurements of GaAs quantum dot

The effects of a vertical electric field on the fine structure splitting of neutral exciton of monolayer fluctuation GaAs quantum dots were investigated. Using the gate voltage between the top gate electrode and the bottom n-GaAs substrate, the fine structure splitting of the neutral exciton was tuned to 15–30 μeV. Photon correlation measurements demonstrate neutral exciton single photon emission and neutral exciton—biexciton cascaded emission.

Transport characterization in nanowires using an electrical nanoprobe

Electrical transport in semiconductor nanowires is commonly measured in a field effect transistor configuration, with lithographically defined source, drain and in some cases, top gate electrodes. This approach is labor intensive, requires high-end fabrication equipment, exposes the nanowires to extensive processing chemistry and places practical limitations on minimum nanowire length. Here we describe an alternative, simple method for characterizing electrical transport in nanowires directly on the growth substrate, without any need for post growth processing. Our technique is based on contacting nanowires using a nano-manipulator probe retrofitted inside of a scanning electron microscope. Using this approach, we characterize electrical transport in GaN nanowires grown by catalyst-free selective epitaxy, as well as InAs and Ge nanowires grown by a Au-catalyzed vapor solid liquid technique. We find that in situations where contacts are not limiting carrier injection (GaN and InAs nanowires), electrical transport transitions from Ohmic conduction at low bias to space-charge-limited conduction at higher bias. Using this transition and a theory of space-charge-limited transport which accounts for the high aspect ratio nanowires, we extract the mobility and the free carrier concentration. For Ge nanowires, we find that the Au catalyst forms a Schottky contact resulting in rectifying current–voltage characteristics, which are strongly dependent on the nanowire diameter. This dependence arises due to an increase in depletion width at decreased nanowire diameter and carrier recombination at the nanowire surface.

NOR-Type Nonvolatile Ferroelectric-Gate Memory Cell Using Composite Oxide Technology

We fabricated a NOR-type memory cell composed of a ferroelectric-gate thin-film transistor (FeTFT) and an insulated gate thin-film transistor (TFT), which were a memory element and a select switch, respectively. The FeTFT consisted of a heteroepitaxially stacked oxide structure of ZnO (n-type semiconductor)/Pb(Zr,Ti)O3 (PZT; ferroelectric)/SrRuO3 (bottom-gate electrode) on a SrTiO3 substrate. An insulated gate stack of Au/Ti (top-gate electrode)/SiNx (insulator) was formed on the ZnO film. The drain electrode of the FeTFT was common to the source electrode of the TFT. The current–voltage (Ids–Vgs) characteristics of the FeTFT exhibited a high ON/OFF ratio of 105 by applying sweeping bottom-gate voltages (Vgs) from -10 to 10 V. After the removal of gate bias, the ON and OFF states were preserved by the remnant polarization of the ferroelectric film. Moreover, the current–voltage characteristics of the TFT exhibited an ON/OFF ratio of 105. The field effect mobility of the TFT was estimated to be 25 cm2 V-1 s-1, which corresponded to an electron mobility of 26 cm2 V-1 s-1 measured for the ZnO film by a van der Pauw method. However, the field effect mobility of the FeTFT, typically 0.1 cm2 V-1 s-1, was quite different from those values. The difference in field effect mobility was attributed to whether current flowed along the ZnO/PZT or SiNx/ZnO interface. We also confirmed the write and read operations of the memory cell using pulse sequences.

Electroluminescent devices based on amorphous SiN/Si quantum dots/amorphous SiN sandwiched structures

A single layer of dense Si quantum dots with average size of 4 nm sandwiched in amorphous SiN layers was prepared by laser crystallization of ultrathin amorphous Si film followed by subsequently thermal annealing. The electroluminescent diodes were fabricated by evaporating Al electrodes on back sides of p-Si substrates and the top surface of samples. Room temperature electroluminescence can be detected with applying the negative voltage around 10V on the top gate electrode and the luminescent intensity is increased with increasing the applied voltage. It was found that the integrated luminescent intensity is linearly proportional to the injection current which suggested the intensity depends on the concentrations of injected carriers after Fowler-Nordheim tunneling through amorphous SiN barriers. The influence of the amorphous SiN with different band gap on the device performance was also discussed briefly.