TiN Capping Layer Research Articles

In-situ deposited anti-aging TiN capping layer for Nb superconducting quantum circuits

Abstract The performance of Nb superconducting quantum devices is predominantly limited by dielectric loss at the metal–air interface, where Nb2O5 is considered the main loss source. Here, we suppress the formation of native oxides by in-situ deposition of a TiN capping layer on the Nb film. With TiN capping layers, no Nb2O5 forms on the surface of the Nb film. The quality factor Q i of the Nb resonator increases from 5.6 × 105 to 7.9 × 105 at low input power and from 6.8 × 106 to 1.1 × 107 at high input power. Furthermore, the TiN capping layer also shows good aging resistance in Nb resonator devices, with no significant performance fluctuations after one month of aging. These findings highlight the effectiveness of TiN capping layers in enhancing the performance and longevity of Nb superconducting quantum devices.

Development of nanometer-thick graphite film extreme ultraviolet pellicle with hydrogen-resistant TiN capping layer

TiN has beneficial physicochemical properties, such as high hardness, good chemical inertness, and good corrosion resistance. TiN has been used for optical filters and protective coatings to exploit these properties. We deposited TiN using atomic layer deposition as a capping layer for a pellicle. We investigated the hydrogen plasma resistance using Raman spectroscopy, transmission electron microscopy, atomic force microscopy, and x-ray photoelectron spectroscopy. As the hydrogen plasma exposure time increased, bonds formed between the TiN film and nitrogen compounds. With long-term exposure, the thickness of the TiN film decreased owing to etching.

Atomic layer deposited TiN capping layer for sub-10 nm ferroelectric Hf0.5Zr0.5O2 with large remnant polarization and low thermal budget

Ferroelectric Hf0.5Zr0.5O2 (HZO) thin films has attracted a large amount of interests in academia and industry. The scaling of the HZO thickness down to the sub-10 nm region with a low thermal budget is essential in practical applications. However, pronounced ferroelectricity in sub-10 nm HZO thin films prepared at a low process temperature is rarely reported. In this paper, significant ferroelectricity is reported in 6 nm HZO thin films by the TiN capping electrode prepared by atomic layer deposition (ALD). Capping the ALD TiN layer leads to the crystallization of an as-deposited amorphous HZO thin film to the ferroelectric orthorhombic phase. The post-annealing treatment at a low temperature of 400 °C contributes to a record remnant polarization (2Pr) of ∼ 51.2 μC/cm2 in sub-10 nm HZO. The mechanisms of the TiN capping effect are investigated based on the TiN capping layers prepared by ALD and sputtering. The distinct ferroelectric properties can be attributed to the formation of a large in-plane tensile stress and the TiOxNy mixed phase by the ALD TiN capping layer. The realization of the low thermal budget and high 2Pr in sub-10 nm HZO thin films by the ALD TiN capping layer is highly promising for next-generation ferroelectric applications.

Paraelectric/antiferroelectric/ferroelectric phase transformation in As-deposited ZrO2 thin films by the TiN capping engineering

Based on the engineering of the TiN capping layer, the tailoring of the crystalline phases and the paraelectric(PE)/antiferroelectric(AFE)/ferroelectric(FE) properties of nanoscale ZrO2 thin films are demonstrated without any post-annealing treatment. The capping by the TiN layer leads to the conversion of ZrO2 from the PE to the AFE electrical characteristics, while the removal of the TiN capping layer results in the AFE-to-FE phase transformation of ZrO2. The nano-beam electron diffraction, high-resolution transmission electron microscopy and X-ray diffraction characterizations identify the presence of the AFE tetragonal and FE orthorhombic phases in ZrO2, and the observations reveal the emergence of the out-of-plane compressive and in-plane tensile strains in the ZrO2 layers by the TiN capping layer as well. The results demonstrate the significant impact of the TiN capping layer effect on the crystalline phases and dielectric properties of nanoscale thin films at a low temperature, which may play an important role in the FE/AFE applications which need a low thermal budget.

Insights Into the Effect of TiN Thickness Scaling on DC and AC NBTI Characteristics in Replacement Metal Gate pMOSFETs

Fast characterization methods are utilized to investigate DC and AC negative bias temperature instability (NBTI) characteristics in pMOSFETs with different TiN capping layer thicknesses ( ${t} _{\mathrm{ TiN}}$ ). The impacts of ${t} _{\mathrm{ TiN}}$ scaling on the threshold voltage shift ( ${\Delta }\text{V}_{\mathrm{ T}}$ ), pre-existing hole traps ( ${\Delta }\text{V}_{\mathrm{ HT}}$ ), generated traps (GTs), and their relative contributions are studied. The time exponents of ${\Delta }\text{V}_{\mathrm{ T}}$ and GTs, and the impacts of stress voltage, temperature, frequency, and duty cycle on the NBTI degradation are analyzed. DC and AC NBTI degradations increase with ${t} _{T}{}_{iN}$ . When ${t} _{\mathrm{ TiN}}$ is scaled down from 3 nm to 1 nm, the maximum operation field is improved by 60%, which originates from the reduction in both ${\Delta }\text{V}_{\mathrm{ HT}}$ and GTs. Moreover, we experimentally demonstrate that bulk trap generation is an ${f}$ -dependent process and that its relative contribution to ${\Delta }\text{V}_{\mathrm{ T}}$ increases with ${t} _{\mathrm{ TiN}}$ , which is an important factor for the improvement of NBTI through ${t} _{\mathrm{ TiN}}$ scaling.

Electron scattering at Co(0001) surfaces: Effects of Ti and TiN capping layers

In situ transport measurements on epitaxial 7.6-nm-thick Co(0001)/Al2O3(0001) films with and without Ti and TiN capping layers during O2 exposure are used to investigate the effects of surface chemistry on electron scattering at Co(0001) surfaces. The Co sheet resistance Rs increases with increasing thickness dTi and dTiN of the Ti and TiN capping layers, saturating at 8% and 31% above the uncoated Co(0001) for dTi > 0.2 nm and dTiN > 0.1 nm, respectively. This increase is attributed to electron scattering into local surface states, which is less pronounced for Ti than TiN. In situ resistance measurements taken during a continuously increasing O2 partial pressure from 0 Pa to 40 Pa indicate a relatively steep 24% increase in Rs at an exposure of ∼50 Pa s, which can be attributed to Co surface oxidation that leads to atomic level roughness and a decrease in the electron scattering specularity p. Ti and TiN cap layers with dTi ≥ 0.5 nm and dTiN ≥ 0.13 nm exhibit no resistance change upon air exposure, indicating suppression of Co oxidation. These results indicate a promising Co–Ti interface with an electron scattering specularity of p = 0.4–0.5, which is retained during oxygen exposure, while, in contrast, electron scattering at the Co–TiN interface is completely diffuse (p = 0), suggesting that Ti barrier layers facilitate higher-conductivity Co interconnects than TiN barriers, as long as the Ti layer is sufficiently thick (dTi ≥ 0.5 nm) to suppress Co oxidation.

Fabrication and Performance of Ti/Al/Ni/TiN Au-Free Ohmic Contacts for Undoped AlGaN/GaN HEMT

We proposed a preparation method of a TiN capping layer compatible with the ohmic contacts process, and demonstrated the Au-free ohmic contacts of an undoped AlGaN/GaN high-electron-mobility transistor (HEMT) with a Ti/Al/Ni/TiN metal structure. TiN was prepared through depositing Ti thin film by a sputtering system and then annealing in N2 ambient by the rapid thermal annealing process. The thickness of Ti/Al, annealing temperature, and annealing time were investigated systematically. Using the Ti/Al/Ni/TiN structure, a low contact resistance ( $3.47 \times 10^{-5}\,\,\Omega $ cm2, $1.1~\Omega \cdot mm$ ) was obtained when annealed at 900 °C for 30 s in N2 ambient, which was comparable with conventional Au-based ohmic contacts ( $3.12 \times 10^{-5} \Omega \cdot cm^{2}$ , $1.05~\Omega \cdot mm$ ). In addition, the Ti/Al/Ni/TiN ohmic contacts showed smooth surface morphology with a surface roughness of 5.89 nm. AlGaN/GaN HEMT, based on Ti/Al/Ni/TiN Au-free ohmic contacts, was also fabricated and exhibited good dc characteristics. The reported Au-free AlGaN/GaN HEMT fabrication process can be used in standard Si fabs without the risk of contamination.

Influence of an ALD TiN capping layer on the PBTI characteristics of n-FinFET with ALD HfO2/TiN-capping/TiAl gate stacks

Influence of an ALD TiN capping layer on the PBTI characteristics of n-FinFET with ALD HfO2/TiN-capping/TiAl gate stacks

Use of Si KLL Auger shifts and the Auger parameter in XPS to distinguish Ti silicides from a Ti/Si mixture in thin films

A particular wafer processing step involves deposition of a Ti thin film (˜6 nm to ˜13 nm) on Si, under processing conditions intended to form a silicide with specific electrical properties. It is difficult, however, to distinguish silicide formation from mere elemental inter-diffusion. Routine laboratory XPS, using an Al X-Ray source(1486.6ev), does have an appropriate probing depth for the film stack involved, but the chemical shifts in Ti (2p) and Si(2p) are too small (<0.3ev), particularly if small charging artifacts might be present. The Si KLL Auger transition, accessed using a Zr X-Ray source (2042.4ev), has much larger shifts. We demonstrate its use to reliably and non-destructively distinguish Ti silicide formation from simple inter-diffusion, even when the layer of interest may lie below a TiN capping layer and some ambient surface oxidation. We also report Auger Parameters and discuss the advantages and disadvantages of their use.

Back-End Integrable On-Chip MIM Decoupling Capacitors Featuring High Capacitance With Ultra-Low Leakage Current by Nitrogen-Incorporated HfZrOx

HfZrOx (HZO) crystallized in orthorhombic phase formed by plasma-enhanced atomic layer deposition (ALD) deposition and subsequent 400 °C annealing with TiN capping layer was employed as the dielectric for on-chip metal-insulator-metal (MIM) decoupling capacitors. With appropriate NH3 plasma treatment on HZO/TiN interface and bulk HZO to respectively, suppress interfacial scavenging effect and passivate defects pertinent to oxygen vacancies, enhanced k value of 28.9, high capacitance of 23.3 fF/μm 2 and low leakage of 0.16 fA/μm 2 at 1 V, 25 °C are achieved. With the plasma treatment, the improved interfacial and bulk quality that are confirmed by transmission electron microscopy and electron energy loss spectroscopy also lead to more desirable reliability of 10-year lifetime at 125 °C. The MIM capacitor technology exhibits performance that is notably advantageous over other high k dielectrics. More importantly, HfO2, ZrO2 and NH3 plasma treatment are all fab-friendly processes, with proper process integration, it is possible to further push the limit of their capabilities to realize decoupling capacitors eligible for sub-7 nm technology.

Nucleation‐Limited Ferroelectric Orthorhombic Phase Formation in Hf0.5Zr0.5O2 Thin Films

AbstractVarious possibilities have been proposed as the cause of the doped‐ or undoped‐HfO2 thin film materials showing unusual ferroelectricity. These assumptions are based on empirical results, yet finding the origin of the unprecedented ferroelectricity within HfO2 has suffered from a serious gap between its theoretical calculation, mostly based on thermodynamic approach and the actual experimental results. To fill the gap, this study proposes to consider the kinetic energy, providing the evidence of the kinetic energy barrier upon a phase transformation from the tetragonal phase to the monoclinic phase affected by the TiN top electrode (capping layer). 10 nm thick Hf0.5Zr0.5O2 thin films are deposited and annealed with or without the TiN capping layer with subsequent annealing at different time and temperature. Arrhenius plot is constructed to obtain the activation energy for the tetragonal‐to‐monoclinic phase transformation by calculating the amount of the transformed phase using X‐ray diffraction pattern. Johnson–Mehl–Avrami and nucleation‐limited transformation models are utilized to describe the characteristic nucleation and growth time and calculate the activation energy for the monoclinic phase transformation of the Hf0.5Zr0.5O2 thin film. Both models demonstrate that the TiN capping layer provides a kinetic energy barrier for tetragonal‐to‐monoclinic phase transformation and enhances the ferroelectric property.

Impact of ALD TiN Capping Layer on Interface Trap and Channel Hot Carrier Reliability of HKMG nMOSFETs

In this letter, the effect of TiN capping layer on interface quality and the channel hot carrier (CHC) reliability of high-k/metal-gate (HKMG) nMOSFET was investigated. Experiments show that the fresh interface trap density was reduced from ${1.83}\times {10}^{{11}}$ to ${7.75}\times {10}^{{10}}$ cm−2 for 1.4 and 2.4 nm ALD TiN capping layers, respectively, while the CHC time-to-failure was worsened by 13%. Combining the chemical analysis by secondary ion mass spectroscopy and the characterization of active energy for trap generation, it is found that the extraordinary chlorine introduced by a ALD TiN capping layer deposition could be responsible for the improved fresh interfacial trap but degraded CHC reliability in HKMG nMOSFETs. The mechanism can be explained by the lower binding energy of Si–Cl than Si–H, which results in more interface passivation but easier to be broken by electrical stress. This finding can provide the guide for the optimization of HKMG process.

Design of electrical probe memory with TiN capping layer

The concept of electrical probe memory using phase-change media has recently received considerable attention due to its promising potential for next-generation data storage device. However, the physical performances of the conventional electrical probe memory are strongly limited by its diamond-like carbon capping layer ascribed to its large contact resistance and sharp difference between the theoretically optimized properties values and the experimentally measured values. Therefore, the diamond-like carbon capping layer is replaced by a titanium nitride layer here, and the modified device architecture is re-optimized by a newly developed three-dimensional model, resulting in a media stack consisting of a 2-nm Ge2Sb2Te5 layer sandwiched by 2-nm titanium nitride layer with an electrical conductivity of 2 × 105 Ω−1 m−1 and a thermal conductivity of 12 W m−1 K−1, and a 40-nm titanium nitride bottom layer with an electrical conductivity of 2 × 106 Ω−1 m−1 and a thermal conductivity of 12 W m−1 K−1. The advantageous features of such a device on the writing of both crystalline and amorphous bits are also demonstrated according to the developed model.

Multi-${V}_{\text{th}}$ Strategies of 7-nm node Nanosheet FETs With Limited Nanosheet Spacing

In this paper, multi-threshold voltage ( V th) scheme of 7-nm node nanosheet FETs (NSFETs) with narrow NS spacing were successfully achieved by metal-gate work function (WF) and channel doping ( $N _{\mathrm{ ch}}$ ) using fully calibrated 3-D TCAD simulations. The limited NS spacing, which allows TiN capping layer only, makes different WF between the edge and the middle part of NS circumference. Unfortunately, this causes non-linear V th shifts and dc performance degradation as a function of WF due to one-side turn-on phenomena between the edge and the middle part. Furthermore, the fixed WF of TiN capping layer limits V th shifts toward ultra-low-power applications. To enable multi- V th of NSFETs, several possible solutions are addressed: changing the $N _{\mathrm{ ch}}$ and the WF of TiN capping layer. The higher $N _{\mathrm{ ch}}$ enables lower off-state current while 50-nm-wide three-stacked NS decreases dc performance variations effectively. Changing the WF of TiN capping layer can extend V th margins, but degrade DC performance as a trade-off. Nonetheless, 7-nm node NSFETs adopting these techniques have multi- V th options to satisfy wide ranges from ultra-low-power to high-performance applications.

Ferroelectric of HfO2 dielectric layer sputtered with TiN or ZrN for sandwich-like metal-insulator-metal capacitors

In this study, metal-insulator-metal (MIM) capacitors, which use HfO2 as the intermediate insulating layer, and TiN or ZrN as the upper/lower capping layers were fabricated to form the sandwich-like structures, i.e. Al/TiN/HfO2/TiN/Mo/p-Si and Al/ZrN/HfO2/ZrN/Mo/p-Si. The crystallization of high-k HfO2 thin-film is induced by high power impulse magnetron sputtering (HIPIMS) during the deposition of TiN and/or ZrN capping layers. The ferroelectric performance became better in both two structures as the thickness of metal nitride layer decreased. As the rapid thermal annealing (RTA) temperature after TiN layer deposition increased, the ferroelectric performance of the structure with TiN layer became better. On the other hand, the structure with ZrN layer exhibited opposite trends. According to X-ray diffraction (XRD) measurement, both TiN and ZrN layers offered stress and produced orthorhombic phase on HfO2 layer. Both two layers at any thicknesses also protected Mo layer from the invasion of Hf atoms. The structure with TiN layer exhibited a higher remanent polarization (Pr) value as the roughness of TiN layer increased. However, the higher the roughness that the structure with ZrN layer had, the worse the ferroelectric performance obtained.

Au-free ohmic Ti/Al/TiN contacts to UID n-GaN fabricated by sputter deposition

The fabrication and characterization of an Au-free Ti/Al/TiN (20/100/100 nm) contact stack to unintentionally doped n-GaN with TiN serving as the diffusion barrier is presented. Sputter deposition and lift-off in combination with post deposition annealing at 850 °C are used for contact formation. After annealing, contact shows ohmic behavior to n-GaN and a specific contact resistivity of 1.60 × 10−3 Ω cm2. To understand the contact formation on the microscopic scale, the contact was characterized by current–voltage measurements, linear transmission line method, X-ray diffraction, transmission electron microscopy, and X-ray photoelectron spectroscopy. The results show the formation of Ti-N bonds at the GaN/Ti interface in the as-deposited stack. Annealing leads to diffusion of Ti, Al, Ga, and N, and the remaining metallic Ti is fully consumed by the formation of the intermetallic tetragonal Al3Ti phase. Native oxide from the GaN surface is trapped during annealing and accumulated in the Al interlayer. The TiN capping layer, however, was chemically stable during annealing. It prevented oxidation of the Ti/Al contact bilayer successfully and thus proved to be a well suitable diffusion barrier with ideal compatibility to the Ti/Al contact metallization.

Study on influences of TiN capping layer on time-dependent dielectric breakdown characteristic of ultra-thin EOT high-k metal gate NMOSFET with kMC TDDB simulations**Project supported by the National High Technology Research and Development Program of China (Grant No. SS2015AA010601), the National Natural Science Foundation of China (Grant Nos. 61176091 and 61306129), and the Opening Project of Key Laboratory of Microelectronics Devices

The thickness effect of the TiN capping layer on the time dependent dielectric breakdown (TDDB) characteristic of ultra-thin EOT high-k metal gate NMOSFET is investigated in this paper. Based on experimental results, it is found that the device with a thicker TiN layer has a more promising reliability characteristic than that with a thinner TiN layer. From the charge pumping measurement and secondary ion mass spectroscopy (SIMS) analysis, it is indicated that the sample with the thicker TiN layer introduces more Cl passivation at the IL/Si interface and exhibits a lower interface trap density. In addition, the influences of interface and bulk trap density ratio Nit/Not are studied by TDDB simulations through combining percolation theory and the kinetic Monte Carlo (kMC) method. The lifetime reduction and Weibull slope lowering are explained by interface trap effects for TiN capping layers with different thicknesses.

Accurate lifetime prediction for channel hot carrier stress on sub-1 nm equivalent oxide thickness HK/MG nMOSFET with thin titanium nitride capping layer

Channel hot carrier (CHC) degradation in sub-1nm equivalent oxide thickness (EOT) HK/MG nMOSFET has been studied in this paper. It is found that the degradation can be divided into two regimes based on stress induced drain-induced-barrier-lowering (DIBL) variation, namely higher stress drain voltage regime and lower stress drain voltage regime. Cause of the division is attributed to different activities of hot carriers. Lifetime prediction excluding higher voltage regime shows to be a more accurate method. In addition, there exists a deviation of degradation trend between 1.4nm TiN and 2.4nm TiN thickness nMOSFET in lower voltage regime. The deviation is attributed to different interface trap generation induced by TiN capping layer in different thickness, which is proved by the charge pumping experiment.

Mechanical properties of low- and high-k dielectric thin films: A surface Brillouin light scattering study

Surface Brillouin light scattering measurements are used to determine the elastic constants of nano-porous low-k SiOC:H (165 nm) and high-k HfO2 (25 nm) as well as BN:H (100 nm) films grown on Si substrates. In addition, the study investigates the mechanical properties of ultra-thin (25 nm) blanket TiN cap layers often used as hard masks for patterning, and their effects on the underlying low-k dielectrics that support a high level of interconnected porosity. Depending on the relative material properties of individual component layers, the acoustic modes manifest as confined, propagating, or damped resonances in the light scattering spectra, thereby enabling the mechanical properties of the ultra-thin films to be determined.

Influence of ultra-thin TiN thickness (1.4 nm and 2.4 nm) on positive bias temperature instability (PBTI) of high-k/metal gate nMOSFETs with gate-last process**Project supported by the National High Technology Research and Development Program of China (Grant No. SS2015AA010601) and the National Natural Science Foundation of China (Grant Nos. 61176091 and 61306129).

The positive bias temperature instability (PBTI) degradations of high-k/metal gate (HK/MG) nMOSFETs with thin TiN capping layers (1.4 nm and 2.4 nm) are systemically investigated. In this paper, the trap energy distribution in gate stack during PBTI stress is extracted by using ramped recovery stress, and the temperature dependences of PBTI (90 °C, 125 °C, 160 °C) are studied and activation energy (Ea) values (0.13 eV and 0.15 eV) are extracted. Although the equivalent oxide thickness (EOT) values of two TiN thickness values are almost similar (0.85 nm and 0.87 nm), the 2.4-nm TiN one (thicker TiN capping layer) shows better PBTI reliability (13.41% at 0.9 V, 90 °C, 1000 s). This is due to the better interfacial layer/high-k (IL/HK) interface, and HK bulk states exhibited through extracting activation energy and trap energy distribution in the high-k layer.