Abstract

Channel hot carrier (CHC) degradation in sub-1nm equivalent oxide thickness (EOT) HK/MG nMOSFET has been studied in this paper. It is found that the degradation can be divided into two regimes based on stress induced drain-induced-barrier-lowering (DIBL) variation, namely higher stress drain voltage regime and lower stress drain voltage regime. Cause of the division is attributed to different activities of hot carriers. Lifetime prediction excluding higher voltage regime shows to be a more accurate method. In addition, there exists a deviation of degradation trend between 1.4nm TiN and 2.4nm TiN thickness nMOSFET in lower voltage regime. The deviation is attributed to different interface trap generation induced by TiN capping layer in different thickness, which is proved by the charge pumping experiment.

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