Timing Paths Research Articles

A Platform of Resynthesizing a Clock Architecture Into Power-and-Area Effective Clock Trees

To trigger events for application-specific data transfer among registers in a multimillion-gate system-on-chip (SoC), various kinds of clock signals, selectively driven by different frequency-dependent sources and/or dividers (DIVs), are usually centralized in one or more clock generation modules, where clock gating cells (CGCs), multiplexers (MUXes) and DIVs are used to create the clocks required by different functional operations in an SoC. These modules will introduce uncommon and longer timing paths for clock propagations and further make the clock tree synthesis (CTS) process become more challenging due to the on-chip-variation (OCV) effects. In addition, high volume of switching activities in the increased number of clock logic cells will consume more power. In this article, a novel design platform, merging and replacing of multiple multiplexers and dividers (MRMMD), is developed to intelligently identify those suspicious clock architectures and resynthesize them into a power-and-area effective and less complicated clock structure. Using our resynthesis platform, not only the number of clock-related timing paths and their corresponding logic levels can be reduced, but also the corresponding analysis and implementations of clock skew minimizations during CTS become much easier. The experimental results implemented in TSMC 55- and 28-nm process nodes on optimizing some industrial clock architectures showed that significant reductions of area, power, latency, skew and clock path, logic level, OCV impact, total wire length, and implementation runtime are achieved using our MRMMD platform.

Calculated Risks: Quantifying Timing Error Probability With Extended Static Timing Analysis

Timing analysis is a key step in the digital design process. By modeling device delay variations statistical static timing analysis (SSTA) reduces pessimism compared to traditional static timing analysis (STA). However, it ignores the circuit’s logic which causes some timing paths to never, or only rarely, be sensitized. We introduce a general timing analysis approach and tool to calculate the probability that individual timing paths are sensitized, enabling the calculation of bounding delay distributions over all input combinations. We show how this analysis is related to the well-known #SAT problem and present approaches to improve scalability, achieving, on average, results 75% to 37% less pessimistic than STA while running 569 to 16 times faster than Monte-Carlo timing simulation.

Methodology for validating Nest Memory Management Unit

The growing demand for performance makes the processor logic design more complex, thereby making post-silicon validation a critical and complex step in processor development life cycle. There are complex units with newer timing and control logic paths which are almost impossible to exercise in regular verification environments. One such unit to cater to newer workloads in recent superscalar processors is the Nest Memory Management Unit (NMMU), a memory management unit for all I/O devices. This paper presents some of the major challenges in validating Nest MMU. A postsilicon validation framework is proposed to mitigate these challenges. An asynchronous non-blocking accelerator job submission model is used in this approach to increase the translation traffic from the agent to NMMU. Core MMU translation is used as the reference model to validate nest MMU. The processor core storage exception handlers are leveraged to minimize the validation tool software development effort and to increase the efficiency of validation as well. This method makes use of an optimized threshold-based checker to detect potential NMMU hardware issues. The proposed methodology has been experimentally evaluated in Power9 NMMU to demonstrate the effectiveness of the method in providing considerable stress to the unit.

QBF-Based Post-Silicon Debug of Speed-Paths Under Timing Variations

Speed-path debugging at the post-silicon stage due to timing variations is a challenging problem in designing high-performance digital circuits. In this paper, we propose an efficient and scalable method for automatic speed-path debugging which is based on quantified Boolean formulas (QBF) to detect multiple erroneous paths when taking into account the timing variations. We have proposed new gate-level timing variation and path slowdown models which enable us to formulate such a debugging problem as a QBF problem. The results on the ISCAS’85 and ISCAS’89 benchmarks show that our method enjoys on average 52.4% decrease in the size model, and 63.1% decrease in debugging time in comparison with existing methods. Moreover in situations where existing methods due to the size explosion of abundant copies cannot be applied, the proposed method detects erroneous gates in a reasonable runtime.

Design of Approximate Circuits by Fabrication of False Timing Paths: The Carry Cut-Back Adder

This paper introduces a novel method for designing approximate circuits by fabricating and exploiting false timing paths, i.e., critical paths that cannot be logically activated. This allows to strongly relax timing constraints while guaranteeing minimal and controlled behavioral change. This technique is applied to an approximate adder architecture, called the Carry Cut-Back Adder (CCBA), in which high-significance stages can cut the carry propagation chain at lower-significance positions. This lightweight approach prevents the logic activation of the carry chain, improving performance and energy efficiency while guaranteeing low worst-case errors. A design methodology is presented along with implementation, error optimization, and design-space minimization. The CCBA is proven capable of extremely high accuracy while displaying significant circuit savings. For a worst case precision of 99.999%, energy savings up to 36% are demonstrated compared with exact adders. Finally, an industry-oriented comparison of 32-bit approximate and truncated adders is carried out for mean and worst-case relative errors. The CCBA outperforms both state-of-the-art and truncated adders for high-accuracy and low-power circuits, confirming the interest of the proposed concept to help building highly-efficient approximate or precision-scalable hardware accelerators.

Activation-Aware Slack Assignment for Time-to-Failure Extension and Power Saving

This paper proposes a mean time-to-failure (MTTF) aware design methodology for minimizing power dissipation while satisfying target chip lifetime. The key contributions of the proposed design methodology are to explicitly introduce MTTF as a design constraint and optimize the design with activation-aware slack assignment (ASA). Conventionally, the gates included in nonintrinsic critical paths are downscaled or replaced with high- $V$ th gates for power savings, where the nonintrinsic critical paths are timing paths which originally had large timing slacks before the downscaling and replacement. On the other hand, ASA gives timing slacks to nonintrinsic critical paths and reduces the number of active paths whose delays are very close to those of intrinsic critical paths whose timing slacks cannot be increased by resynthesis and sizing. The proposed optimization includes both pre-ASA circuit design and ASA implementation. The former pre-ASA design prepares several design candidates that laid out with different timing constraints and selects the most promising candidate regarding power. For this selection, every candidate is analyzed to estimate minimum supply voltage after ASA that can achieve the target MTTF. Then, the proposed methodology selects a set of flip-flops for ASA using integer linear programming, such that it reduces the sum of gatewise failure probability maximumly, and performs ASA. We evaluate MTTF of circuits with and without ASA and examine how much power saving can be obtained while satisfying the target MTTF, e.g., 10 years. Evaluation results show that the circuits with ASA achieve up to 49.6% power saving.

The mathematics of market timing.

Market timing is an investment technique that tries to continuously switch investment into assets forecast to have better returns. What is the likelihood of having a successful market timing strategy? With an emphasis on modeling simplicity, I calculate the feasible set of market timing portfolios using index mutual fund data for perfectly timed (by hindsight) all or nothing quarterly switching between two asset classes, US stocks and bonds over the time period 1993–2017. The historical optimal timing path of switches is shown to be indistinguishable from a random sequence. The key result is that the probability distribution function of market timing returns is asymmetric, that the highest probability outcome for market timing is a below median return. Put another way, simple math says market timing is more likely to lose than to win—even before accounting for costs. The median of the market timing return probability distribution can be directly calculated as a weighted average of the returns of the model assets with the weights given by the fraction of time each asset has a higher return than the other. For the time period of the data the median return was close to, but not identical with, the return of a static 60:40 stock:bond portfolio. These results are illustrated through Monte Carlo sampling of timing paths within the feasible set and by the observed return paths of several market timing mutual funds.

Separating Timing, Movement Conditions and Individual Differences in the Analysis of Human Movement.

A central task in the analysis of human movement behavior is to determine systematic patterns and differences across experimental conditions, participants and repetitions. This is possible because human movement is highly regular, being constrained by invariance principles. Movement timing and movement path, in particular, are linked through scaling laws. Separating variations of movement timing from the spatial variations of movements is a well-known challenge that is addressed in current approaches only through forms of preprocessing that bias analysis. Here we propose a novel nonlinear mixed-effects model for analyzing temporally continuous signals that contain systematic effects in both timing and path. Identifiability issues of path relative to timing are overcome by using maximum likelihood estimation in which the most likely separation of space and time is chosen given the variation found in data. The model is applied to analyze experimental data of human arm movements in which participants move a hand-held object to a target location while avoiding an obstacle. The model is used to classify movement data according to participant. Comparison to alternative approaches establishes nonlinear mixed-effects models as viable alternatives to conventional analysis frameworks. The model is then combined with a novel factor-analysis model that estimates the low-dimensional subspace within which movements vary when the task demands vary. Our framework enables us to visualize different dimensions of movement variation and to test hypotheses about the effect of obstacle placement and height on the movement path. We demonstrate that the approach can be used to uncover new properties of human movement.

Timing Path-Driven Cycle Cutting for Sequential Controllers

Power and performance optimization of integrated circuits is performed by timing-driven algorithms that operate on directed acyclic graphs. Sequential circuits and circuits with topological feedback contain cycles. Cyclic circuits must be represented as directed acyclic graphs to be optimized and evaluated using static timing analysis. Algorithms in commercial electronic design automation tools generate the required acyclic graphs by cutting cycles without considering timing paths. This work reports on a method for generating directed acyclic circuit graphs that do not cut the specified timing paths. The algorithm is applied to over 125 benchmark designs and asynchronous handshake controllers. The runtime is less than 1 second, even for even the largest published controllers. Circuit timing graphs generated using this method retain the necessary timing paths, which enables circuit validation and optimization employing the commercial tools. Additional benefits show these designs are on an average a third in size, operate 33.3% faster, and consume one-fourth the energy.

A practical automated timing and physical design implementation methodology for the synchronous asynchronous interface and multi-voltage domain in high-speed synthesis

In a high-speed synthesis design environment, designers struggle to ensure that multi-clock and multi-power interfaces are designed, placed, connected and timed correctly. Identifying and applying proper timing constraints such as “no cycle stealing” at synchronous and asynchronous domain interfaces in macro synthesis, unit and chip timing are essential. Standard cell library characterization, for multi-power and timing challenges due to an additional delay for level translator circuitry, demand careful implementation in a high-speed synthesis methodology. We propose a pseudo algorithm and methodology for synthesis and timing that will correctly identify synchronous and asynchronous interfaces. Our proposed methodology shows how these interface paths should be excluded from “cycle stealing” and yet, take full advantage of slack borrowing for the rest of the design. We find ∼28% and ∼80% timing path improvement in two of the units for IBM's Power8TM (P8) microprocessor. As an alternative to high-effort custom design, we develop a synthesis-based physical design methodology that incorporates the use of a level translator, enabling designers to address major issues that encompass dual-voltage solutions in high-speed design. We find ∼50% physical design effort savings using this methodology. P8 is a 12-core, 649 mm2, 4.2B transistor chip fabricated in IBM's 22-nm Silicon On Insulator (SOI) technology, which is fully functional to support a wide range of high performing systems with an operating frequency greater than 4.5GHz.

A Method to Design Single Error Correction Codes With Fast Decoding for a Subset of Critical Bits

Single error correction (SEC) codes are widely used to protect data stored in memories and registers. In some applications, such as networking, a few control bits are added to the data to facilitate their processing. For example, flags to mark the start or the end of a packet are widely used. Therefore, it is important to have SEC codes that protect both the data and the associated control bits. It is attractive for these codes to provide fast decoding of the control bits, as these are used to determine the processing of the data and are commonly on the critical timing path. In this brief, a method to extend SEC codes to support a few additional control bits is presented. The derived codes support fast decoding of the additional control bits and are therefore suitable for networking applications.

A Flexible, Event-Driven Digital Filter With Frequency Response Independent of Input Sample Rate

This paper presents a clockless digital filter able to process inputs of different rates and formats, synchronous or asynchronous, with no adjustment needed to handle each input type. The filter is designed using a mix of asynchronous and real-time digital hardware, and for this reason relies on neither a clock nor the input data rate for setting its frequency response. The modular architecture of the filter, including delay segments with separated data and timing paths and a pipelined multi-way adder, allows easy extensions for different data widths. The filter was used as part of an ADC/DSP/DAC system which maintains its frequency response intact for varying sample rates without requiring any internal change. This property is not possible for any synchronous DSP system. The 16-tap, 8-bit FIR filter, integrated in a 130 nm CMOS process, includes on-chip automatic delay tuning, and for certain inputs, has signal-to-error ratio which exceeds that of clocked systems.

Correlation Analysis of Multiple Sensors for Industrial Gas Turbine Compressor Blade Health Monitoring

This paper summarizes an analysis of data obtained from an instrumented compressor of an operational, heavy duty industrial gas turbine; the goal of the aforementioned analysis is to understand some of the fundamental drivers, which may lead to compressor blade vibration. Methodologies are needed to (1) understand the fundamental drivers of compressor blade vibration, (2) quantify the severity of “events,” which accelerate the likelihood of failure and reduce the remaining life of the blade, and (3) proactively detect when these issues are occurring so that the operator can take corrective action. The motivation for this analysis lies in understanding the correlations between different sensors, which may be used to measure the fundamental drivers and blade vibrations. In this study, a variety of dynamic data was acquired from an operating engine, including acoustic pressure, bearing vibration, tip timing, and traditional gas path measurements. The acoustic pressure sensors were installed on the first four compressor stages, while the tip timing was installed on the first stage only. These data show the presence of rotating stall instabilities in the front stages of the compressor, occurring during every startup and shutdown, and manifesting itself as increased amplitude oscillations in the dynamic pressure measurements, which are manifested in blade and bearing vibrations. The data that lead to these observations were acquired during several startup and shutdown events, and clearly show that the amplitude of these instabilities and the rpm at which they occur can vary substantially.

Impact of Local Interconnects on Timing and Power in a High Performance Microprocessor

In nanometer technologies, local interconnects are believed to cause a major impact on timing and power in VLSI circuits. To assess the impact of the interconnects on timing and power in a real high performance microprocessor design in a quantitative manner, this article presents results from an extensive study carried out on RTL-to-layout synthesized blocks in a 45-nm technology core. The study shows that the interconnects in these blocks account for 30% of the cycle time, on an average, on the worst internal timing paths and contribute nearly one-third to the power dissipation. This points to severity of impact due to the interconnects in today's high performance designs.

Concurrent Path Selection Algorithm in Statistical Timing Analysis

Circuit timing is becoming more and more uncertain under greater process variation as technology scales. Given the fault probability of each timing path and their statistical correlation from a statistical timing framework, the path selection problem for delay faults has a nature similar to the problem of designing a portfolio of stocks or assets or determining the size of bets in gambling to minimize risk. This observation allows us to develop a very different path selection approach from the conventional ones. If selection of k paths is required in a set of paths, we partition the set into two path sets and determine how many paths should be selected in each path set out of the k paths based on the probabilities of each path set containing faulty paths. We recursively continue this process, which results in the paths to be targeted during tests. The partitioning is easily performed because the paths are already grouped into the depth-first search tree based on their suffix or prefix. Experimental results show that the proposed algorithm can effectively use the correlation to generate high-quality path sets. In addition, we study the issues that occur after automatic test pattern generation on the selected paths, and discuss possible solutions to them.

Low Cost Concurrent Error Masking Using Approximate Logic Circuits

With technology scaling, logical errors arising due to single-event upsets and timing errors arising due to dynamic variability effects are increasing in logic circuits. Existing techniques for online resilience to logical and timing errors are limited to detection of errors, and often result in significant performance penalty and high area/power overhead. This paper proposes approximate logic circuits as a design approach for low cost concurrent error masking. An approximate logic circuit predicts the value of the outputs of a given logic circuit for a specified portion of the input space, and can indicate uncertainty about the outputs over the rest of the input space. Using portions of the input space that are most vulnerable to errors as the specified input space, we show that approximate logic circuits can be used to provide low overhead concurrent error masking support for a given logic circuit. We describe efficient algorithms for synthesizing approximate circuits for concurrent error masking of logical and timing errors. Results indicate that concurrent error masking based on approximate logic circuits can mask 88% of targeted logical errors for 34% area overhead and 17% power overhead, 100% timing errors on all timing paths within 10% of the critical path delay for 23% area overhead and 8% power overhead, and 100% timing errors on all timing paths within 20% of the critical path delay for 42% area overhead and 26% power overhead.

High throughput VLSI architecture for H.264/AVC context-based adaptive binary arithmetic coding (CABAC) decoding

Context-based adaptive binary arithmetic coding (CABAC) is the major entropy-coding algorithm employed in H.264/AVC. In this paper, we present a new VLSI architecture design for an H.264/AVC CABAC decoder, which optimizes both decode decision and decode bypass engines for high throughput, and improves context model allocation for efficient external memory access. Based on the fact that the most possible symbol (MPS) branch is much simpler than the least possible symbol (LPS) branch, a newly organized decode decision engine consisting of two serially concatenated MPS branches and one LPS branch is proposed to achieve better parallelism at lower timing path cost. A look-ahead context index (ctxIdx) calculation mechanism is designed to provide the context model for the second MPS branch. A head-zero detector is proposed to improve the performance of the decode bypass engine according to UEGk encoding features. In addition, to lower the frequency of memory access, we reorganize the context models in external memory and use three circular buffers to cache the context models, neighboring information, and bit stream, respectively. A pre-fetching mechanism with a prediction scheme is adopted to load the corresponding content to a circular buffer to hide external memory latency. Experimental results show that our design can operate at 250 MHz with a 20.71k gate count in SMIC18 silicon technology, and that it achieves an average data decoding rate of 1.5 bins/cycle.

Testing of defects in Si semiconductor apparatus by using single-photon detection

The failure analysis of semiconductor apparatus is very needed for ensuring product quality, which can find several types of defects in the semiconductor apparatus. A new testing method for the defects in Si semiconductor apparatus is presented in this paper, the method makes use of photon emissions to find out the failure positions or failure components by taking advantage of the infrared photo emission characteristics of semiconductor apparatus. These emitted photons carry the information of the apparatus structure. If there are defects in the apparatus, these photons can help in understanding the apparatus properties and detecting the defects. An algorithm for the generation of circuit input vectors are presented in this paper to enhance the strength of the emitted photons for the given components in the semiconductor apparatus. The multiple-valued logic, the static timing analysis and path sensitizations, are used in the algorithm. A lot of experimental results for the Si semiconductor apparatus show that many types of defects such as contact spiking and latchup failure etc., can be detected accurately by the method proposed in this paper.

Timing–driven variation–aware synthesis of hybrid mesh/tree clock distribution networks

Clock skew variations adversely affect timing margins, limiting performance, reducing yield, and may also lead to functional faults. Non-tree clock distribution networks, such as meshes and crosslinks, are employed to reduce skew and also to mitigate skew variations. These networks, however, increase the dissipated power while consuming significant metal resources. Several methods have been proposed to trade off power and wires to reduce skew. In this paper, an efficient algorithm is presented to reduce clock skew variations while minimizing power dissipation and metal area overhead. With a combination of nonuniform meshes and unbuffered trees (UBT), a variation-tolerant hybrid clock distribution network is produced. Clock skew variations are selectively reduced based on circuit timing information generated by static timing analysis (STA). The skew variation reduction procedure is prioritized for critical timing paths, since these paths are more sensitive to skew variations. A framework for skew variation management is proposed. The algorithm has been implemented in a standard 65nm cell library using standard EDA tools, and tested on several benchmark circuits. As compared to other nonuniform mesh construction methods that do not support managed skew tolerance, experimental results exhibit a 41% average reduction in metal area and a 43% average reduction in power dissipation. As compared to other methods that employ skew tolerance management techniques but do not use a hybrid clock topology, an 8% average reduction in metal area and a 9% average reduction in power dissipation are achieved.

Variation-Tolerant Architecture for Ultra Low Power Shared-L1 Processor Clusters

In this brief, we propose a variation-tolerant architecture for shared-L1 processor clusters working at near-threshold (NT). Our variation-tolerant technique is able to compensate the effect of delay variations, which are exacerbated by moving to the NT region, on the processor to memory communication by adding one or two stages of controllable pipelines. Moreover, we propose a reconfigurable address-interleaving technique, which enables us to shut down some of the memory blocks if they are either too slow due to the variation or not needed by the application (to reduce power consumption). Experimental results show that our speed adaptation approach is able to compensate up to 90% degradation in the request path with less than 2% hardware overhead for a shared-L1 cluster with 16 processors and 32 memory banks. The configurable interleaving technique has an overhead of 10% on the request timing path of a 16 × 32 interconnection network.