Abstract
Speed-path debugging at the post-silicon stage due to timing variations is a challenging problem in designing high-performance digital circuits. In this paper, we propose an efficient and scalable method for automatic speed-path debugging which is based on quantified Boolean formulas (QBF) to detect multiple erroneous paths when taking into account the timing variations. We have proposed new gate-level timing variation and path slowdown models which enable us to formulate such a debugging problem as a QBF problem. The results on the ISCAS’85 and ISCAS’89 benchmarks show that our method enjoys on average 52.4% decrease in the size model, and 63.1% decrease in debugging time in comparison with existing methods. Moreover in situations where existing methods due to the size explosion of abundant copies cannot be applied, the proposed method detects erroneous gates in a reasonable runtime.
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