Time-to-digital Converter Research Articles

A progressive phase multiple-injection locking technique for jitter suppression in voltage-controlled ring oscillator

ABSTRACT This paper presents a jitter reduction technique for a voltage-controlled ring oscillator (VCRO). This technique is useful in employing VCRO-based circuits like Analog to Digital Converter (ADC), Phase Locked Loop (PLL), and various time-based circuits whose performance is severely degraded by jitter accumulation, an inherent property of VCRO. In the proposed technique, a 1-bit time-to-digital converter (TDC) is used to extract information about jitter with a sensitivity of 4ps/bit. The rise in phase detector output bit leads VCRO to work in Progressive Phase Multi-Injection Locking (PPM-IL) mode until VCRO gets jitter-free. The proposed work is designed in SCL 180 nm CMOS technology at 1.8 V supply. After enabling the proposed technique, the RMS jitter reduces from 7.436 ps to 1.198ps for VCRO running at 63 MHz and consumes a total power of 1.112 mW.

Design and Validation of a Long-Range Streak-Tube Imaging Lidar System with High Ranging Accuracy

The Streak-Tube Imaging Lidar (STIL) has been widely used in high-precision measurement systems due to its ability to capture detailed spatial and temporal information. In this paper, we proposed a ranging measurement method that integrates a Time-to-Digital Converter (TDC) with a streak camera in a remote STIL system. In this method, the TDC accurately measures the trigger pulse time, while the streak camera captures high time-resolution images of the laser echo, thereby enhancing both measurement accuracy and range. A corresponding ranging model is developed for this method. To validate the system’s performance, an outdoor experiment covering a distance of up to 6 km was conducted. The results demonstrate that the system achieved a distance measurement accuracy of 0.1 m, highlighting its effectiveness in long-range applications. The experiment further confirms that the combination of STIL and TDC significantly enhances accuracy and range, making it suitable for various long-range, high-precision measurement tasks.

A Fully Synthesizable Fractional-N Digital Phase-Locked Loop with a Calibrated Dual-Referenced Interpolating Time-to-Digital Converter to Compensate for Process–Voltage–Temperature Variations

This paper presents advancements in the performance of digital phase-locked loop (DPLL)s, with a special focus on addressing the issue of required gain calibration in the time-to-digital converter (TDC) within phase-domain DPLL structures. Phase-domain DPLLs are preferred for their simplicity in implementation and for eliminating the delta–sigma modulator (DSM) noise inherent in conventional fractional-N designs. However, this advantage is countered by the critical need to calibrate the gain of the TDC. The previously proposed dual-interpolated TDC(DI-TDC) was proposed as a solution to this problem, but strong spurs were still generated due to the TDC resolution, which easily became non-uniform due to PVT variation, degrading performance. To overcome these problems, this work proposes a DPLL with a new calibration system that ensures consistent TDC resolution matching the period of the digitally controlled oscillator (DCO) and operating in both the foreground and background, thereby maintaining consistent performance despite PVT variations. This study proposes a DPLL using a calibrated dual-interpolated TDC that effectively compensates for PVT variations and improves the stability and performance of the DPLL. The PLL was fabricated in a 28-nm CMOS process with an active area of only 0.019 mm2, achieving an integrated phase noise (IPN) performance of −17.5 dBc, integrated from 10 kHz to 10 MHz at a PLL output of 570 MHz and −20.5 dBc at 1.1 GHz. This PLL operates within an output frequency range of 475 MHz to 1.1 GHz. Under typical operating conditions, it consumes only 930 µW with a 1.0 V supply.

Novel Power-Efficient Fast-Locking Phase-Locked Loop Based on Adaptive Time-to-Digital Converter-Aided Acceleration Compensation Technology

This paper proposes an adaptive acceleration lock compensation technology for phase-locked loops (PLLs) based on a novel dual-mode programmable ring voltage-controlled oscillator (ring-VCO). In addition, a time-to-digital converter (TDC) is designed to accurately quantify the phase difference from the phase frequency detector (PFD) in order to optimize the dead-zone effect while dynamically switching an auxiliary charge pump (CP) module to realize fast phase locking. Furthermore, a TDC-controlled three/five-stage dual-mode adaptively continuously switched VCO is proposed to optimize the phase noise (PN) and power efficiency, leading to an optimal performance tradeoff of the PLL. Based on the 180 nm/1.8 V standard CMOS technology, the complete PLL design and a corresponding simulation analysis are implemented. The results show that, with a 1 GHz reference signal as the input, the output frequency is 50–324 MHz, with a wide tuning range of 260 MHz and a low phase noise of −98.07 dBc/Hz@1 MHz. The key phase-locking time is reduced to 1.11 μs, and the power dissipation is lowered to 1.86 mW with a layout area of 66 μm × 128 μm. A significantly remarkable multiobjective performance tradeoff with topology optimization is realized, which is in contrast to several similar design cases of PLLs.

Area-Efficient Mixed-Signal Time-to-Digital Converter Integration for Time-Resolved Photon Counting.

Digital histogram generation for time-resolved measurements with single-photon avalanche diode (SPAD) sensors requires the storage of many timestamp signals. This work presents a mixed-signal time-to-digital converter (TDC) that uses analog storage to achieve an area-efficient design that can be integrated in large SPAD arrays. Fabricated using a 150 nm CMOS process, the prototype occupies an area of only 18.3 µm × 36.5 µm, a notable size reduction compared to conventional designs. The experimental results demonstrated high performance, with an integral nonlinearity (INL) of 0.35/0.14 least significant bit (LSB) and a differential nonlinearity (DNL) of 0.14/-0.12 LSB. In addition, the proposed TDC can support the construction of histograms comprising up to 512 bins, making it an effective solution to accommodate a wide range of resolution requirements. Validated in a point-of-care (PoC) device for fluorescence lifetime measurements, it distinguished between lifetimes of approximately 4.1 ns, 3.6 ns and 80 ns with the Alexa Fluor (AF) 546 and 568 dyes and Quantum Dot (QD) 705, respectively. The analog storage design and area-efficient architecture offer a novel approach to integrating TDCs in SPAD-based systems, with potential applications in medical diagnostics and beyond.

A cost-effective field-programmable-gate-array-based pulse processor for biomedical imaging applications

ObjectiveThis paper presents the design and evaluation of a cost-effective, high-spatial resolution, multichannel, field-programmable gate array (FPGA)-based readout system for Positron Emission Tomography (PET) detectors suitable for clinical and pre-clinical work in cancer and other diseases. A key challenge in PET imaging is the precise measurement of the time of arrival and energy of gamma photons originating from positron annihilation, along with the position of interaction within the detector. These parameters enhance image quality by improving coincidence detection, excluding Compton-scattered photons, and improving system spatial resolution. We developed a 16-channel readout system using single silicon photomultiplier (SiPM) element readout for efficient and precise energy, time, and position measurements. Each channel incorporates an FPGA-based sigma-delta analog-to-digital converter (ΣΔ-ADC) and tapped delay line (TDL) based time-to-digital converter (TDC) for timing and energy estimation. Performance characterization of the system was performed through simulation, electronically generated waveform, and actual PET detector signals from three different single scintillation crystals of face dimensions 3 × 3 mm2 and depths of 5 and 20 mm coupled to a 3 × 3 mm2 SiPM. We also constructed and tested a modular PET detector with a 10x10 array of 1.2x1.2x14 mm³ LSO crystals coupled to a 4x4 SiPM array of 3 × 3 mm2 elements. Best energy resolution was 9.3% at the 511 KeV photopeak and best coincidence timing resolution (CTR) was 210 ± 3.5 ps. Our system balances cost-effectiveness with performance and contributes to developments in PET signal acquisition and detector technology.

Low-Resource Time-to-Digital Converters for Field Programmable Gate Arrays: A Review.

A fundamental aspect in the evolution of Time-to-Digital Converters (TDCs) implemented within Field-Programmable Gate Arrays (FPGAs), given the increasing demand for detection channels, is the optimization of resource utilization. This study reviews the principal methodologies employed for implementing low-resource TDCs in FPGAs. It outlines the foundational architectures and interpolation techniques utilized to bolster TDC performances without unduly burdening resource consumption. Low-resource Tapped Delay Line, Vernier Ring Oscillator, and Multi-Phase Shift Counter TDCs, including the use of SerDes, are reviewed. Additionally, novel low-resource architectures are scrutinized, including Counter Gray Oscillator TDCs and interpolation expansions using Process-Voltage-Temperature stable IODELAYs. Furthermore, the advantages and limitations of each approach are critically assessed, with particular emphasis on resolution, precision, non-linearities, and especially resource utilization. A comprehensive summary table encapsulating existing works on low-resource TDCs is provided, offering a comprehensive overview of the advancements in the field.

A Low-Power Optoelectronic Receiver IC for Short-Range LiDAR Sensors in 180 nm CMOS.

This paper presents a novel power-efficient topology for receivers in short-range LiDAR sensors. Conventionally, LiDAR sensors exploit complex time-to-digital converters (TDCs) for time-of-flight (ToF) distance measurements, thereby frequently leading to intricate circuit designs and persistent walk error issues. However, this work features a fully differential trans-impedance amplifier with on-chip avalanche photodiodes as optical detectors so that the need of the following post-amplifiers and output buffers can be eliminated, thus considerably reducing power consumption. Also, the combination of amplitude-to-voltage (A2V) and time-to-voltage (T2V) converters are exploited to replace the complicated TDC circuit. The A2V converter efficiently processes weak input photocurrents ranging from 1 to 50 μApp which corresponds to a maximum distance of 22.8 m, while the T2V converter handles relatively larger photocurrents from 40 μApp to 5.8 mApp for distances as short as 30 cm. The post-layout simulations confirm that the proposed LiDAR receiver can detect optical pulses over the range of 0.3 to 22.8 m with a low power dissipation of 10 mW from a single 1.8 V supply. This topology offers significant improvements in simplifying the receiver design and reducing the power consumption, providing a more efficient and accurate solution that is highly suitable for short-range LiDAR sensor applications.

The ATLAS RPC Phase-II upgrade for High Luminosity LHC era

Resistive Plate Chambers (RPC) detectors play a crucial role in triggering events containing muons in the central region of ATLAS. In view of the High Luminosity-LHC program, the existing RPC system, consisting of six independent cylindrical detector layers each providing a full space time localization of hits, is currently undergoing a significant upgrade. In the next few years, 306 triplets of new generation RPCs will be installed in the innermost region of the ATLAS Muon Barrel Spectrometer, increasing from 6 to 9 the number of tracking layers, doubling the trigger lever arm. This allows a substantial enhancement of the present trigger redundancy, increasing the coverage from 76% to approximately 96%. Fitting new chambers in the narrow space left in ATLAS inner barrel was a challenge, achieved by optimizing RPC materials and thickness, featuring a 1 mm gas gap (instead of 2 mm), and 1.4 mm resistive electrodes (instead of 1.8 mm) while reaching an high rate capability. To achieve such results, a 100 ps precise Time-to-Digital Converter (TDC) has been integrated in the front-end electronics ASIC. The expected time resolution of a single 1 mm RPC gas gap is approximately 300 ps, and the possibility of a stand-alone Time of Flight measurement will have a huge impact on ATLAS searches for massive long-lived particles. An overview and the present status of the ATLAS RPC Phase-II project will be presented.

Hybrid ALM-DSP TDC in Intel Arria 10 FPGA

The article presents the first implementation of a time-to-digital converter (TDC) using a digital signal processing (DSP) block from an Intel field-programmable gate array (FPGA) device. The design and configuration capabilities of the DSP blocks of the leading FPGA manufacturers, AMD and Intel, are compared in the context of time/digital conversion. Next, three variants of TDCs are presented. The problem of ultra-wide bins observed in both the classic version of the converter based on the Adaptive Logic Modules (ALM) and the version built using only DSP blocks has been mitigated in a hybrid variant, combining both solutions. The proposed variant of the hybrid ALM-DSP TDC implemented in Arria 10 FPGA from Intel (20 nm process node) achieved a resolution of 2.1 ps, a single-shot-precision better than 6.36 ps and reduced the maximum differential nonlinearity (DNL) error from 74.5 ps to 12.7 ps.

An ADPLL-Based GFSK Modulator with Two-Point Modulation for IoT Applications.

To establish ubiquitous and energy-efficient wireless sensor networks (WSNs), short-range Internet of Things (IoT) devices require Bluetooth low energy (BLE) technology, which functions at 2.4 GHz. This study presents a novel approach as follows: a fully integrated all-digital phase-locked loop (ADPLL)-based Gaussian frequency shift keying (GFSK) modulator incorporating two-point modulation (TPM). The modulator aims to enhance the efficiency of BLE communication in these networks. The design includes a time-to-digital converter (TDC) with the following three key features to improve linearity and time resolution: fast settling time, low dropout regulators (LDOs) that adapt to process, voltage, and temperature (PVT) variations, and interpolation assisted by an analog-to-digital converter (ADC). It features a digital controlled oscillator (DCO) with two key enhancements as follows: ΔΣ modulator dithering and hierarchical capacitive banks, which expand the frequency tuning range and improve linearity, and an integrated, fast-converging least-mean-square (LMS) algorithm for DCO gain calibration, which ensures compliance with BLE 5.0 stable modulation index (SMI) requirements. Implemented in a 28 nm CMOS process, occupying an active area of 0.33 mm2, the modulator demonstrates a wide frequency tuning range of from 2.21 to 2.58 GHz, in-band phase noise of -102.1 dBc/Hz, and FSK error of 1.42% while consuming 1.6 mW.

High Spatial Resolution Detector System Based on Reconfigurable Dual-FPGA Approach for Coincidence Measurements.

Time-resolved spectroscopic and electron-ion coincidence techniques are essential to study dynamic processes in materials or chemical compounds. For this type of analysis, it is necessary to have detectors capable of providing, in addition to image-related information, the time of arrival for each individual detected particle ("x, y, time"). The electronics capable of handling such sensors must meet requirements achievable only with time-to-digital converters (TDC) with a resolution on the order of tens of picoseconds and the use of a field-programmable gate array (FPGA) to manage data acquisition and transmission. This study introduces the design and implementation of an innovative TDC based on two FPGAs working symbiotically with different tasks: the first (AMD/Xilinx Artix® 7) directly implements a TDC, aiming for a temporal precision of 12 picoseconds, while the second (Intel Cyclone® 10) manages the acquisition and connectivity with the external world. The TDC has been optimized to operate on eight channels (+ sync) simultaneously but is potentially extendable to a greater number of channels, making it particularly suitable for coincidence measurements where it is necessary to temporally correlate multiple pieces of information from various measurement systems.

Analytical description of the time-over-threshold method based on time properties of plastic scintillators equipped with silicon photomultipliers

A new highly granular neutron detector (HGND) for the identification and energy measurement of neutrons produced in nucleus–nucleus interactions at the BM@N experiment, Dubna, Russia, at energies up to 4 AGeV is under development. The detector consists of approximately 2000 fast plastic scintillators, each with dimensions of 40 × 40 × 25 mm3, equipped with SiPM (Silicon Photomultiplier) with an active area of 6 × 6 mm2. The signal readout from these scintillators will employ a single-threshold multichannel Time-to-Digital Converter (TDC) to measure their response time and charge using the time-over-threshold (ToT) method. This article focuses on the analytical description of the signals from the plastic scintillator detectors equipped with silicon photomultipliers. This description is crucial for establishing the ToT to charge relationship and implementing slewing correction techniques to improve the time resolution of the detector.

A novel detector for 4D tracking in particle therapy

An innovative beam monitor for particle therapy applications was developed to count protons and carbon ions in clinical beams and was integrated with a Time-to-Digital Converter (TDC) to add the measurement of particles’ crossing time. The detector exploits strip-segmented planar silicon sensors with an active thickness of a few tens of μm and the front-end electronics is based on a 24-channel ASIC (named ABACUS) for the discrimination of the particles’ signals. The proton counting efficiency shows a dependence on the beam energy because of transversal dimension and pile-up effects, whereas an efficiency between 94 and 98 % with lower energy dependence is found for carbon ions. The time measurements with the TDC allow for the study of the time interval between consecutive particles in one strip, which appears to be compatible with the radio-frequency period of the synchrotron. These results indicate that thin silicon sensors and custom front-end readout with high counting rate capability allow for a full 4D tracking of clinical ion beams, opening the way to future technologies for online monitoring systems.

Design of a high-precision time-to-digital converter in an Elitestek Ti60 field-programmable-gate-array.

The time-to-digital converter (TDC) implemented in a field-programmable-gate-array has garnered widespread attention due to its flexibility and high-performance capabilities. However, issues such as non-uniformity, the bubble in the tapped delay line, and the presence of certain ultra-wide delay units can significantly compromise the precision and nonlinearity of the TDC. In this paper, we propose a high-precision TDC in an Elitestek Ti60 FPGA, effectively eliminating the adverse effects of non-uniformity, the bubble, and certain ultra-wide delay units. The TDC is constructed with a 318-stage delay chain and operates at a low system clock frequency of 150MHz. The least significant bit (LSB) of the TDC is 21.92ps. The differential nonlinearity (DNL) is between (-0.976, 1.615) LSB and the integral nonlinearity (INL) is between (-1.446, 2.678) LSB. The TDC achieves a root-mean-square error of 14.783ps when utilized for measuring various time intervals.

A Configurable Resolution Time-to-Digital Converter with Low PVT Sensitivity for LiDAR Applications

This paper presents an all-digital and configurable resolution time-to-digital converter (TDC) with low process–voltage–temperature (PVT) sensitivity for light detection and ranging (LiDAR) applications. The proposed TDC offers configurable resolution, allowing it to provide an appropriate conversion resolution according to the system’s requirements, thereby optimizing overall system performance. In addition, because the proposed TDC has high immunity to process–voltage–temperature (PVT) variations, it provides more stable time-converting results. The proposed design uses 0.18 μm CMOS technology, and the measurement results demonstrate a resolution ranging from 36 ps to 1193 ps, with a conversion range from 0.1 ns to 36 ns and an average error of 20.59 ps. Furthermore, the proposed TDC is implemented in an all-digital manner, making it highly suitable for system integration.

Entropy Analysis of FPGA Interconnect and Switch Matrices for Physical Unclonable Functions

Random variations in microelectronic circuit structures represent the source of entropy for physical unclonable functions (PUFs). In this paper, we investigate delay variations that occur through the routing network and switch matrices of a field-programmable gate array (FPGA). The delay variations are isolated from other components of the programmable logic, e.g., look-up tables (LUTs), flip-flops (FFs), etc., using a feature of Xilinx FPGAs called dynamic partial reconfiguration (DPR). A set of partial designs is created to fix the placement of a time-to-digital converter (TDC) and supporting infrastructure to enable the path delays through the target interconnect and switch matrices to be extracted by subtracting out common-mode delay components. Delay variations are analyzed in the different levels of routing resources available within FPGAs, i.e., local routing and across-chip routing. Data are collected from a set of Xilinx Zynq 7010 devices, and a statistical analysis of within-die variations in delay through a set of the randomly-generated and hand-crafted interconnects is presented.

Programmable delay cell based area efficient time-mode smart temperature sensor exploiting channel length modulation coefficient λ

This work presents an all-digital Programmable Delay Cell (PDC)-based time-domain smart temperature sensor exploiting the channel length modulation coefficient λ. For the first time the work has been described to establish the choice of multimode conversion options in the time-domain architecture of temperature sensor. The sensor incorporates a PDC and a time-to-digital converter (TDC) for the generation of temperature code. The different channel lengths of the PDC and Gated Ring Oscillator (GRO) delay elements of the TDC ensure the precise operation of the sensor. The proposed design provides a novel approach for the generation of variable resolution options having different sampling rates. At 90-nm CMOS process and 1.1 V supply voltage, the sensor occupies 0.015 mm2 and operates over a span of −60 °C to 120 °C. Additionally, multimode conversion time allows the sensor to be tuned to a small value of energy/conversion at 27 °C. This confirms to 0.38 nJ and 3.13 nJ at modes M0 and M7, respectively. Besides the sensor obtains a resolution 0.747 °C and 0.093 °C at a conversion time of 0.669 μs and 5.5 μs, respectively.

Power-efficient 12-bit 800 MS/s voltage-time hybrid domain ADC with split TDC in 28 nm CMOS

In this paper, an 800 MS/s 12bit voltage-time hybrid domain ADC is presented. A four-channel split time-to-digital converter (TDC) is proposed in the first-stage sub-TDC, effectively reducing the impact of skew error. A configurable time amplifier (TA) is proposed to pre-configure the discharge voltage, optimizing the conversation rate and power consumption. The hybrid domain ADC verified in a 28-nm CMOS process with a core area of 0.033 mm2, which achieves 65.66 dB SNDR and 72.16 dB SFDR while consuming 7.93 mW from a single 0.9-V supply, resulting in Walden figure-of-merit (FoM) values of 6.34 fJ/conversion-step.

A 0.055 mm2 Total Area Triple-Loop Wideband Fractional-N All-Digital Phase-Locked Loop Architecture for 1.9–6.1 GHz Frequency Tuning

This paper presents a wideband fractional-N all-digital phase-locked loop (WBPLL) architecture featuring a triple-loop configuration capable of tuning frequencies from 1.9 to 6.1 GHz. The first and second loops, automatic frequency control (AFC) and counter-assisted phase-locked loop (CAPLL), respectively, perform coarse locking, while the third loop employs a digital sub-sampling architecture without a frequency divider for fine locking. In this third loop, fractional-N frequency synthesis is achieved using a delta-sigma modulator (DSM) and digital-to-time converter (DTC). To minimize area, digital modules such as counters, comparators, and differentiators used in the AFC and CAPLL loops are reused. Furthermore, a moving average filter (MAF) is employed to reduce the frequency overlap ratio of the digitally controlled oscillator (DCO) between the second and third loops, ensuring stable loop switching. The total power consumption of the WBPLL varies with the frequency range, consuming between 8.8 mW at the WBPLL minimum output frequency of 1.9 GHz and 12.8 mW at the WBPLL maximum output frequency of 6.1 GHz, all at a 1.0 V supply. Implemented in a 28 nm CMOS process, the WBPLL occupies an area of 0.055 mm2.