Time-zero Dielectric Breakdown Research Articles

The Influence of Extended Defects in 4H-SiC Epitaxial Layers on Gate Oxide Performance and Reliability

For the ongoing commercialization of power devices based on 4H-SiC, increasing the yield and improving the reliability of these devices is becoming more and more important. In this investigation, gate oxide on 4H-SiC was examined by time-zero dielectric breakdown (TZDB) and constant current stress (CCS) time-dependent dielectric breakdown (TDDB) method in order to get insights into the influence of the epitaxial defects on the gate oxide performance and reliability. For that purpose, MOS capacitors with different gate oxides have been fabricated. Crystal defects in the epitaxial layers have been detected and mapped by ultraviolet photoluminescence (UVPL) and interference contrast (DIC) imaging. The results of the comparison of electrical data and surface mapping data indicate a negative influence on the leakage current behavior for some extended epitaxial defects. Results from TDDB measurement indicated numerous extrinsic defects, which can be traced back to gate oxide processing conditions and defect densities.

Improving the reliability of MOS capacitor on 4H-SiC (0001) with phosphorus diffused polysilicon gate

The interface states and reliability of 4H-SiC metal-oxide-semiconductor field effect transistors (MOSFETs) with thermal gate oxides have been researched widely. Several reports have researched the gate oxide process itself, but the effects of subsequent processes should not be ignored. In this paper, the reliability of thermal gate oxide films followed by polysilicon gate (poly-gate) process, which are widely used in MOSFET manufacture, and Al gates were compared. The poly-gate samples markedly affected the performance measured by time-zero dielectric breakdown and time-dependent dielectric breakdown methods because the phosphorus content diffused during poly-gate formatting; this was especially advantageous in reducing leakage current and improving the charge-to-breakdown (Q BD). After electronic characteristics measurements, scanning electron microscopy cross-sections were also used to analyze the breakdown mechanism. We observed an intermediate layer between the Al gate and the oxide that may cause the barrier height to be smaller than that of the poly-gate. The Al work function and polysilicon Fermi level determine the gate leakage currents and the resultant gate oxide reliability, whereas the Al2O3 gate sample has a smaller work function offset (0.7 eV) than ideal Al gate and poly-gate samples. The results imply that the reliability of the Al gate samples may be an intrinsic problem.

Reliability Study of 1T1C FeRAM Arrays With Hf0.5Zr0.5O₂ Thickness Scaling

We have reported that film thickness scaling of ferroelectric Hf0.5Zr0.5O2 (HZO) allows hafnium-based one-transistor and one-capacitor (1T1C) ferroelectric random-access memory (FeRAM) to obtain higher cycling tolerance for hard breakdown with lower voltage operation in prior reports. This paper is an extension of the previous works including a review of recent works on FeRAM-related devices from a film thickness scaling point of view. We experimentally verified the cycling tolerance advantage of film thickness scaling by 1T1C FeRAM array with different HZO thicknesses of 8 nm and 10 nm using different small capacitors areas (0.20, 0.40, and 1.00 lm2) at practical operation conditions for the first time, demonstrating higher reliability at the 8-nm sample with smaller capacitance area. To support the result, time zero dielectric breakdown (TZDB) and time dependent dielectric breakdown (TDDB) were conducted for both 8-nm and 10a-nm samples.

Pre-Deposition Interfacial Oxidation and Post-Deposition Interface Nitridation of LPCVD TEOS Used as Gate Dielectric on 4H-SiC

In this work, the influence of pre-deposition interfacial oxidation or post-deposition interface nitridation on the performance of 4H-SiC MOS capacitors was investigated. The gate oxide was deposited by LPCVD using TEOS as a precursor. Interface breakdown strength was derived from leakage current and Time-Zero Dielectric Breakdown characteristics whereas interface quality was assessed by the determination of interface state density from the comparison of quasi-static and high frequency capacitance-voltage characteristics using high-low method. In the experimental results, it is demonstrated that the gate oxide deposited by LPCVD using TEOS which is post-deposition annealed in nitric oxide ambient is advantageous for trench-gate MOSFET due to its effectiveness for improving the interface quality and oxide reliability, whereas pre-deposition interfacial oxidation is deleterious to interface state density and breakdown strength.

Al(ON) gate dielectrics for 4H-SiC MOS devices

Abstract The gate dielectrics for silicon carbide based MOS devices are still crucial for their performance and reliability. Conventional thermal oxides have a poor interface quality and a low dielectric constant. To mitigate the issues brought about by conventional thermal oxidation, Al(ON) based on atomic layer deposition (ALD) technique is proposed and studied in terms of interface state density and dielectric strength/reliability. To make comparison, the results of AlN and Al2O3 grown using the same ALD technique, are included as well. It is shown that by incorporating of nitrogen/AlN, Al(ON) can reduce interface state density and border trap density. In addition, its dielectric strength/reliability in terms of time-zero-dielectric breakdown (TZDB) also improves.

Effects of Microwave Annealing on High-k Dielectric HfO₂ Thin Films.

In this study, the effect of microwave annealing (MWA), which has been attracting considerable attention as a low-thermal-budget method, on the high-k materials required for next-generation ultrahigh-integration semiconductor devices is investigated. Metal-oxide-semiconductor (MOS) capacitor-structure devices are fabricated using HfO₂ films, which are typical high-k materials; post deposition annealing (PDA) is then performed by MWA and compared to conventional thermal annealing (CTA). The current-voltage (I-V) and capacitance-voltage (C-V) characteristics of the fabricated HfO₂ MOS capacitors are measured to evaluate the leakage current, time-zero dielectric breakdown (TZDB), time-dependent dielectric breakdown (TDDB), and frequency dispersion. Compared to the as-deposited state, the PDA-treated HfO₂ dielectric film is found to have reduced trap density, improved dielectric breakdown, frequency dispersion, and lifetime. In particular, the high-k HfO₂ thin films treated with MWA exhibit excellent surface properties, including a low root-mean square roughness (Rq) of 0.141 nm, thickness of 49.3 nm, and low inter face trap density (Dit) of 7.82 × 1012 cm-2eV-1 and electrical properties such as a high breakdown electric field (EBD) of 10 MV/cm, and high breakdown to charge (QBD) of 1,000 C/cm². As a result, the MWA-treated high-k HfO₂ thin films are smoother and denser than the CTA-treated thin films, and show better electrical properties and reliability, suggesting that the defects at Si the interface as well as in the high-k films are effectively removed.

Influence of curvature induced stress on first principle calculation and the reliability of 4H-SiC (0001) thermally grown SiO2 gate oxide

Gate oxide films on silicon carbide (SiC) markedly affect the performance of SiC metal-oxide-semiconductor field effect transistors (MOSFETs). We used current-voltage (I–V) measurements to investigate the influence of curvature induced stress/strain on the breakdown electric field and the charge-to-breakdown (QBD) at SiO2/SiC, defined here as time-zero dielectric breakdown and time-dependent dielectric breakdown, respectively. The curvature of the epitaxy wafers was characterized by a thin film stress measurement system. The compression/tensile curvature decreased EBD and QBD during the dry thermal oxidation process. Furthermore, first-principle calculations suggested that the energy levels of the samples were related to the lattice constants of the SiC crystal, indicating that stress mainly affected the SiO2/SiC interface. We suggest that a “stress free” oxide film might be the best choice for SiC-MOSFET applications.

Effects of cesium ion implantation on the mechanical and electrical properties of porous SiCOH low-k dielectrics

In this work, the authors report an investigation of the effects of cesium (Cs) ion implantation on both porogen-embedded and ultraviolet (UV)-cured (porous) SiCOH films. For porogen-embedded SiCOH, it was found that Cs ion implantation can greatly improve the elastic modulus. It can also increase the time-zero dielectric breakdown (TZDB) strength. It also leads to an increase in the k-value for medium and high Cs doses, but for low Cs doses, the k-value decreased compared with its pristine counterpart. For UV-cured SiCOH, it was found that Cs-ion implantation does not improve the elastic modulus. It also leads to lower TZDB field strength and much higher k-values than its pristine counterpart. These effects can be understood by examining the changes in chemical bonds. This treatment is shown to have the potential to help solve the problem of the demand for lower k-values and the concomitant weak mechanical strength of SiCOH.

Analysis Self-Healing of Gate Leakage Current due to Oxide Traps to Improve Reliability of Gate Electrode

To achieve robust SiC-MOSFET, reliability of the gate insulator was investigated in terms of gate electrode edge treatment. Analytical calculation showed that r should be larger than the thickness of gate insulator to relax the electric field concentration. We obtained the rounded gate edge by dry oxidation at 1000°C, while oxidation at 800°C had it sharpened. Former samples exhibited low leakage current with Time-Zero-Dielectric-Breakdown (TZDB) measurement. Ig consisted of Fowler-Nordheim (FN) tunneling current for Vg > 0, and it includes excess components for Vg < 0. We confirmed that they occurred at the gate edge and that they coursed positively charged trap centers in oxide near poly-Si/SiO2 interface which caused local barrier lowering. Electron injection removed them by tunneling/recombination process, which followed tunneling-front model.

Combined Effect of Rapid Thermal Annealing and Crystal Nature on the Gate Oxide Reliability of Czochralski Silicon

Internal gettering (IG) of metallic impurities (MI) in Czochralski silicon (CZ-Si) is one of the key techniques in modern microelectronic engineering to manufacture high-performance devices with high process yield. Various silicon substrates such as EPI wafers with heavily boron-doped substrates, ion-implanted wafers, and rapid-thermal annealing (RTA) treated wafers have been used to enhance IG ability [1-2] and retain denuded zone (DZ) for the active area of devices. Especially, RTA-treatment is an easy way to form IG and DZ simultaneously with a rapid heat process that injects the intrinsic point defects, mainly vacancies, into the bulk. However, it was reported that vacancy clusters, or ‘nano voids’ whose size was less than 50nm [2-3] could be formed in the near-surface region after RTA process via vacancy self-trapping [4], which can possibly degrade the performance and yield of device. In this study, we investigated the effect of RTA treatment on the gate oxide reliability and their relation to the crystal nature, i.e., as-grown point defect distribution in silicon wafers.As shown in Fig. 1 a), we performed the Cu-contamination method [5] on the prepared samples to verify the crystal nature of each sample. After that, we separated the samples into two groups whether they treated by RTA or not, and carried out time-zero dielectric breakdown (TZDB) reliability tests on the patterned poly-Si/oxide/Semiconductor capacitors with the gate oxide thickness of 10 nm. As shown in Fig. 1 b), distribution of TZDB failed cell on the wafer was closely related to the crystal nature. Moreover, it was revealed that a vacancy-dominant region tends to have lower breakdown field than an interstitial-dominant region. These phenomena were only found in RTA-treated wafers and entire fail rate was drastically increases when RTA effect was combined with vacancy-dominated region, which was shown in Fig. 1 b). We assumed that as-grown vacancies contained in the vacancy-dominated region tend to enhance the supersaturation of vacancy beneath the oxide-semiconductor interface, so the formation of nano voids was accelerated and the breakdown field was lowered due to the presence of such defects. A detailed mechanism of the experimental result will be discussed. Figure 1. a) Crystal nature measured by Cu contamination method and b) TZDB frequency with or without RTP

Non uniform thermal oxidation of SiC and its impact on electrical characteristics

The surface and interface roughnesses of SiO2 films thermally grown on 4H-SiC were investigated by atomic force microscopy. The roughness increases with oxide thickness in the initial oxidation stage, and it saturates at a certain thickness. An increase in roughness reflects nonuniform thermal oxidation. In addition, the two-dimensional fluctuation of oxide film thickness becomes marked for the thin film. Furthermore, current density vs voltage characteristics were investigated using MOS capacitors with various oxide thicknesses. The dispersion of the leakage current was found to be related to the oxide surface and interface roughnesses. On the other hand, time-zero dielectric breakdown voltage showed no relation to the roughness.

Investigation of the Interface Quality and Reliability of 4H-SiC MOS Structure with NO and Forming Gas Annealing Treatment

Effects of NO and forming gas annealing treatment on the interface quality and reliability of 4H-SiC MOS were systematically studied by low temperature conductance measurements in combination with time-zero dielectric breakdown and time-dependent dielectric breakdown methods. The interface trap density (Dit) showed no obvious reduction after forming gas annealing, and the values of Dit decreased significantly after combined NO and forming gas annealing treatment. The F-N barrier height, electric field to breakdown (Ebd) and charge to breakdown (Qbd) of the MOS structure increased from 2.42 eV, 10 MV/cm, 1mC/cm2 to 2.62 eV, 10.7 MV/cm, 78mC/cm2 after forming gas annealing. The values of F-N barrier height, Ebd and Qbd for MOS capacitors with combined NO and forming gas annealing treatment are 2.69 eV, 10.2 MV/cm, and 24mC/cm2. These results suggest that forming gas annealing is more effective in reliability improvement. While when considering the interface trap density, it seems that combined NO and forming gas annealing treatment is a better choice.

Effects of cesium ion-implantation on mechanical and electrical properties of organosilicate low-k films

The effects of cesium (Cs) ion-implantation on uncured plasma-enhanced chemical-vapor-deposited organosilicate low dielectric constant (low-k) (SiCOH) films have been investigated and compared with an ultraviolet (UV) cured film. The mechanical properties, including the elastic modulus and hardness, of the SiCOH low-k films are improved by up to 30% with Cs implantation, and further up to 52% after annealing at 400 °C in a N2 ambient for 1 h. These improvements are either comparable to or better than the effects of UV-curing. They are attributed to an enhancement of the Si-O-Si network structure. The k-value of the SiCOH films increased slightly after Cs implantation, and increased further after annealing. These increases are attributed to two carbon-loss mechanisms, i.e., the carbon loss due to Si-CH3 bond breakage from implanted Cs ions, and the carbon loss due to oxidation during the annealing. The time-zero dielectric breakdown strength was improved after the Cs implantation and the annealing, and was better than the UV-cured sample. These results indicate that Cs ion implantation could be a supplement to or a substitution for the currently used UV curing method for processing SiCOH low-k films.

Effect of Post Plasma Oxidation on Ge Gate Stacks Interface Formation

This work investigates the application of slot plane antenna plasma oxidation (SPAO) during dielectric depositionto processTiN/AlO/ZrO2/Ge MOS capacitors. The impact of SPAO exposure on effective oxide thickness (EOT), leakage current, interface state density (D it), C-V hysteresis, oxide breakdown characteristics have been studied. Considerable degradation of electrical properties has been observed with SPAO being performed before AlO/ZrO2 gate stack deposition. When SPAO is performed in between AlO/ZrO2deposition, moderate increase in EOT and significant decrease in D it was observed, which can be attributed to the formation of a thicker GeOX layer. On the other hand, when SPAO is performed after the deposition of both the high-k layers, higher D it was observed suggesting that a thinner GeOX layer formation. Time zero dielectric breakdown (TZDB) characteristics indicate that plasma exposure after and in between AlO/ZrO2 deposition enhances the dielectric quality by film densification due to plasma exposure. It was demonstrated that improved dielectric and interface quality can be achieved when ALD-AlO/ZrO2 gate stacks were exposed to SPAO.

Lateral Non-Uniformity Reduction by Compensatory Metal Embedded in MOS Structure with Ultra-Thin Anodic Oxide

Lateral non-uniformity (LNU) of gate dielectric has been a serious problem in modern metal-oxide-semiconductor (MOS) devices [1], [2]. It was found the LNU became more severe after adopting the post-metalization annealing (PMA) due to possible spiking of metal. The interface of metal and gate dielectric was believed to be uneven after PMA. In this work, a method to ameliorate the lateral uniformity in MOS capacitors was proposed. By utilizing the anodic oxidation compensation technique to form a compensatory aluminum layer embedded in MOS structure, obvious improvement in lateral oxide uniformity was observed. The schematic of anodic oxidation compensation is shown in Fig. 1. Accordingly, two batches of MOS capacitors with ultra-thin anodic oxide with equivalent oxide thickness (EOT) ranging from 2 nm to 3.4 nm was prepared for comparison. One is denoted as MOS (MOS stands for the simple Al/SiO2/Si(p) structure), while the other one is denoted as EAMOS (EAMOS stands for Al/Al2O3/Al/SiO2/Si(p) structure with compensatory embedded aluminum). From our previous work, it is known that the electrical characteristics of MOS capacitors in accumulation regime are area-dependent [3]. Hence, the electrical characteristics in accumulation regime are practical for examining the degree of LNU. Fig. 2 shows the current-voltage (I-V), current density-voltage (J-V) and capacitance per unit area-voltage (C’-V) characteristics of both devices. It is obvious that the area-dependence is applied much better in EAMOS devices, which clearly indicates the reduction of LNU. Furthermore, in order to verify the uniformity improvement in whole samples, the percentage dispersions of different device areas of current density and capacitance per unit area in accumulation regime with varied EOT’s are illustrated in Fig. 3. In Fig. 3, for each EOT, the quantity of dispersion of MOS devices is larger than the value of EAMOS devices. Fig. 3(a) shows that the average percentage dispersion of MOS devices for capacitance per unit area with various EOT’s is 3.95%, which is larger than the value of 2.28% of EAMOS devices. Fig. 3(b) shows that the average percentage dispersion of MOS devices for current density with various EOT’s is 90.33%, whereas the value of EAMOS devices (27.7%) is much smaller. These results further serve as the evidences of lessening of LNU. In addition, the breakdown behaviors also point out the improvement in oxide uniformity. Fig. 4 shows the characteristics of time-zero dielectric breakdown (TZDB) of thirteen identical devices for both MOS and EAMOS samples. The values of breakdown voltage for EAMOS devices are more consistent (-4 V to -5 V), while the values for MOS devices range from -2.5 V to -5 V, which are comparatively divergent. Furthermore, currents at -2 V and -8 V are more congruous for EAMOS devices. Consequently, these results give another support to the improved oxide uniformity. Finally, benefited from the reduction of LNU, the lateral distribution of vertical electric field must be more uniform. So when biasing at inversion regime, we believed that the induced minority carriers would distributed more uniform in lateral direction. Therefore, the lateral electric field induced by the non-uniformity of minority carriers would be attenuated. So relieved from the disturbance of lateral Coulomb force, the response of minority carriers to the small signal of gate voltage is believed to be more significant in the EAMOS devices than the MOS devices. Fig. 5 shows the capacitance-voltage (C-V) characteristic of both MOS and EAMOS devices with EOT of 3.4 nm and various frequencies. It is obvious that the frequency response of inversion capacitance is more significant for the EAMOS device than the MOS device. This outcome is consistent with the explanation given above, and it is of use for the circuit design consideration in MOS-based devices. This work was supported by the Ministry of Science and Technology of Taiwan, ROC, under Contract No. NSC 102-2221-E-002-183-MY3 and MOST 103-2622-E-002-031.

Improvement in the breakdown endurance of high-κ dielectric by utilizing stacking technology and adding sufficient interfacial layer.

Improvement in the time-zero dielectric breakdown (TZDB) endurance of metal-oxide-semiconductor (MOS) capacitor with stacking structure of Al/HfO2/SiO2/Si is demonstrated in this work. The misalignment of the conduction paths between two stacking layers is believed to be effective to increase the breakdown field of the devices. Meanwhile, the resistance of the dielectric after breakdown for device with stacking structure would be less than that of without stacking structure due to a higher breakdown field and larger breakdown power. In addition, the role of interfacial layer (IL) in the control of the interface trap density (Dit) and device reliability is also analyzed. Device with a thicker IL introduces a higher breakdown field and also a lower Dit. High-resolution transmission electron microscopy (HRTEM) of the samples with different IL thicknesses is provided to confirm that IL is needed for good interfacial property.

Performance and breakdown behavior of graphene field-effect transistors with thin gate oxides

Reactive ion etching is employed to fabricate graphene field-effect transistors (GFETs) with different thicknesses of SiO2 dielectric. The output characteristic of the GFETs with 10 nm gate oxide demonstrates that the gate supply voltage range is from −3.5 to 3.5 V, which is suitable for use in MEMS/NEMS devices, while the supply voltage range of the GFET with 300 nm SiO2 is from −100 to 100 V. The GFET with 10 nm SiO2 reduces the gate supply voltage and the performance is similar to GFET with 300 nm SiO2. The position of the Dirac point depends on several factors, but the surfactant on SiO2 may be the main one. Reliability of thin oxides in GFETs is an important concern. After the time-zero dielectric breakdown of 10 nm SiO2, there is an electric current flowing though the graphene sheet when drain voltage is not applied to the device. This phenomenon may be attributed to the Schottky-like diode of graphene/10 nm SiO2/silicon interfaces. This study also provides a method to identify whether the graphene transistor is damaged or not.

Effect of POCl<sub>3</sub> Annealing on Reliability of Thermal Oxides Grown on 4H-SiC

We have evaluated the reliability of POCl3-annealed oxides on 4H-SiC using time-zero dielectric breakdown (TZDB), constant current time-dependent dielectric breakdown (CC-TDDB), and high-frequency capacitance-voltage (C-V) measurements after electron injection. The POCl3 annealing does not deteriorate oxide breakdown field very much, still keeping an average value of larger than 9 MV/cm. However, the electron injection into POCl3-annealed oxide brings negative charges easily. From the C-V measurements, the POCl3-annealed capacitors were found to indicate a large positive flatband voltage shift after electron injection. Phosphorus atoms in the oxide may be related to the trapping site of injected electrons. The distribution and density of phosphorus in the oxide should be optimized to realize highly reliable 4H-SiC MOSFETs with high performance.

Electrical and Reliability Analysis for GDH High-k Films After Rapid Thermal Annealing

The amorphous HfO2 doped Gd2O3 (GDH) film has been grown on p-type Si (001) substrates by radio frequency co-sputtering, and the thickness of GDH film was 4.4nm. The results of electrical tests showed that the ΔVFB of C-V curves reduced from 170mV to 40mV, dielectric constant increased from 19.6 to 21.3, and relaxation phenomena decreased after RTA. I-V curves showed that the leakage current density of GDH film was reduced from 9.6×10-4 A/cm2 to 1.3×10-5 A/cm2 after Rapid Thermal Annealing (RTA). The reliability studies on GDH gate dielectric show that the Time Zero Dielectric Breakdown (TZDB) was mainly caused by the accumulation of positive charges.

1.4kV Double-Implanted MOSFETs Fabricated on 4H-SiC(000-1)

1.2 mm × 1.2 mm and 2.7 mm × 2.7 mm silicon carbide double-implanted metal-oxide-semiconductor field-effect transistors (DIMOSFETs) were fabricated on 4H-SiC (000-1) carbon face. 1.2 mm × 1.2 mm DIMOSFETs were characterized from room temperature to 150°C. At room temperature, the specific on-resistance of this MOSFET was 5.7 mΩcm2 at a gate bias of 20 V and a drain voltage of 1.0 V. The blocking voltage of this MOSFET was 1450 V based on the avalanche current. At 150 °C, the specific on-resistance increased from 5.7 mΩcm2 to 9.1 mΩcm2 and the threshold voltage decreased from 4.9 V to 4.1 V. The blocking voltage increased from 1450V to 1500V. 2.7 mm × 2.7 mm DIMOSFETs were also characterized at room temperature. They showed a specific on-resistance of 8.0 mΩcm2 at a gate bias of 20 V and a drain voltage of 1 V. The blocking voltage of this device was 1550 V, which was determined by the avalanche current. The time-zero dielectric breakdown (TZDB) and time-dependent dielectric breakdown (TDDB) characteristics of 180 μm × 180 μm MOS capacitor were estimated. At room temperature (RT), TZDB was 9.3 MV/cm and the charge to breakdown value of 63% cumulative failure (Qbd) was 72 C/cm2. The temperature dependence of Qbd measurements showed that it deceased from 72 C/cm2 at RT to 14 C/cm2 at 250 °C. Switching characteristics of 1.2 mm × 1.2 mm DIMOSFETs were obtained by the double-pulse measurements. The turn-on time and the turn-off time were 36 nsec and 53 nsec, respectively.