Abstract
To achieve robust SiC-MOSFET, reliability of the gate insulator was investigated in terms of gate electrode edge treatment. Analytical calculation showed that r should be larger than the thickness of gate insulator to relax the electric field concentration. We obtained the rounded gate edge by dry oxidation at 1000°C, while oxidation at 800°C had it sharpened. Former samples exhibited low leakage current with Time-Zero-Dielectric-Breakdown (TZDB) measurement. Ig consisted of Fowler-Nordheim (FN) tunneling current for Vg > 0, and it includes excess components for Vg < 0. We confirmed that they occurred at the gate edge and that they coursed positively charged trap centers in oxide near poly-Si/SiO2 interface which caused local barrier lowering. Electron injection removed them by tunneling/recombination process, which followed tunneling-front model.
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