Performance and breakdown behavior of graphene field-effect transistors with thin gate oxides

Abstract

Reactive ion etching is employed to fabricate graphene field-effect transistors (GFETs) with different thicknesses of SiO2 dielectric. The output characteristic of the GFETs with 10 nm gate oxide demonstrates that the gate supply voltage range is from −3.5 to 3.5 V, which is suitable for use in MEMS/NEMS devices, while the supply voltage range of the GFET with 300 nm SiO2 is from −100 to 100 V. The GFET with 10 nm SiO2 reduces the gate supply voltage and the performance is similar to GFET with 300 nm SiO2. The position of the Dirac point depends on several factors, but the surfactant on SiO2 may be the main one. Reliability of thin oxides in GFETs is an important concern. After the time-zero dielectric breakdown of 10 nm SiO2, there is an electric current flowing though the graphene sheet when drain voltage is not applied to the device. This phenomenon may be attributed to the Schottky-like diode of graphene/10 nm SiO2/silicon interfaces. This study also provides a method to identify whether the graphene transistor is damaged or not.