Time-to-digital Converter Channels Research Articles

A high-density, 129-channel time-to-digital converter in FPGA for trigger-less data acquisition systems

This paper presents a high-density,129-channel, dual-‘hit’ FPGA-based time-to-digital converter (TDC) developed to implement the trigger-less data acquisition (DAQ) system for the Iron Calorimeter (ICAL) detector of the India-based Neutrino Observatory (INO) experiment. In this trigger-less DAQ scheme, the arrival time of signals from all the detector channels, about 3.6 million channels in the case of the INO-ICAL experiment, is required to be measured. This work, therefore, aimed at the development of a low-power, high-density TDC with uniform performance across the channels in the low-cost Spartan-6 FPGA. This TDC is based on tapped delay line (TDL) interpolation technique built using CARRY4 elements of the FPGA in the Spartan-6 FPGA-based DAQ system. In this TDC, a method for measuring the time-of-arrival of both the rising edge and subsequent falling edge (dual-hit) using a single channel is developed, thus allowing pulse width measurements. Here, a resource and power-aware design methodology is developed to arrive at the optimum values of the total number of delay elements in the TDL and clock frequency, facilitating the implementation of a large number of identical TDC channels. Further, in order to meet the area and timing constraints of the high-density TDC, semi-automatic placement scripts are developed with careful partitioning of the TDC channels. These aspects resulted in an implementation of the TDC with a least significant bit (LSB) resolution of 84.4 ps ± 2.5 ps, a dynamic range of 40 μs, time precisions (σ) across the channels in the range of 42 ps (0.49 LSB) to 58 ps (0.68 LSB), differential nonlinearity (DNL) of ±0.5 LSB and integral nonlinearity (INL) of [-0.49,0.84] LSB with a low power consumption of 7 mW per channel.

A Reconfigurable 5-Channel Ring-Oscillator-Based TDC for Direct Time-of-Flight 3D Imaging

Time-correlated single-photon counting (TCSPC) 3D imaging requires the digitization of photon arrival times across an array of single-photon avalanche diodes (SPADs). The most critical performance metrics of time-to-digital converters (TDC) in TCSPC applications are their conversion rate (CR), area, and power consumption. This paper presents a multi-channel RObased TDC architecture whose power consumption scales with its configurable resolution for power-sensitive applications. Further power savings are achieved by sharing one RO among multiple TDC channels. We have demonstrated that sharing one RO among five channels reduces the power consumption by more than 75 relative to non-shared architectures. Here, a 5-channel 12-bit TDC is fabricated in 65 nm CMOS with an area of 1920 um2 per channel. It demonstrates CR up to 125 MHz and offers a resolution configurable over the range of 24-133 ps. At a CR of 125 MHz, the TDC power consumption per channel is 0.1 mW and 1 mW per channel at 133 ps and 24 ps resolution, respectively.

A 4.32-ps precision Time-to-Digital Convertor using multisampling wave union method on a 28-nm FPGA

In this paper, a fully implemented field programmable gate array (FPGA) based time-to-digital converter (TDC) using multisampling wave union method (MSWU) is proposed to get higher measurement precision with lower resource utilization. Different from the previously published works based on wave union methods, an inverter-chain-based wave launcher is introduced to generate more low-jitter edges in the same operation range. Meanwhile, a new de-bubble solution combining with offline bin alignment and online bin sorting is applied to eliminate severe bubbles in FPGAs of advanced manufacturing technologies. The proposed TDCs are verified on a Virtex-7 (28 nm) of FPGA development board VC707. According to test results, the average measurement precision and mean resolution reach 4.32 ps and 0.82 ps, respectively with [-0.98;3.43] LSB DNL and [-6.06;34.1] LSB INL. A complete TDC channel only uses 831 D-type flip-flops (DFFs), 1305 look-up tables (LUTs) and 6 block random access memories (BRAMs) of 36k bits.

A ring-oscillator based multi-mode time-to-digital converter on Xilinx Kintex-7 FPGA

Taking the system clock as the reference, a ring-oscillator based Vernier-type time stamping method is proposed for the implementation of time-to-digital converters (TDCs) on field programmable gate array (FPGA). A module with this method called time-marker is implemented on a Xilinx Kintex-7 FPGA and tested with 43 ps time resolution and less than 50 ns measurement dead time. To illustrate this time-marker can be used as the building block for TDC construction to provide high time measurement performance with low resource consumption, a multi-mode TDC using eight time-markers is implemented with performance evaluation. The TDC has three flexible configuration modes for performance enhancements in three aspects. In the multi-channel mode, it becomes eight independent TDC channels with average 34 ps time interval RMS precision and 50 ns measurement dead time; in the high-precision mode, it is one TDC channel with 14 ps RMS precision and 50 ns measurement dead time; and in the high-throughput mode, it is one TDC channel with 33 ps RMS precision and 6.25 ns measurement dead time. In addition, the temperature dependence of the performance is evaluated.

Ring-Oscillator-Based High Accuracy Low Complexity Multichannel Time-to-Digital Converter Architecture for Field-Programmable Gate Arrays

This article proposes and validates a low complexity multichannel ring-oscillator (RO)-based time-to-digital converter (TDC) architecture for field-programmable gate arrays (FPGAs). Channels of that TDC are mainly composed of look-up Tables (LUTs) configured as embedded memories. The channels share the same ring oscillator. A previously proposed delay tuning method was used to increase the overall accuracy by balancing the TDC channels. Compared to previously reported TDCs, the proposed architecture consumes fewer resources without degrading performances. A nine-channel TDC was implemented in a Zynq-7 Xilinx FPGA. Single-shot precision of 92.7 ps and accuracy of 92.9 ps were achieved, while consuming 1.49% and 1.31% of the available LUTs and FFs of a ZYNQxc7z010-3clg400 Xilinx FPGA, respectively.

A high resolution time-to-digital-convertor based on a carry-chain and DSP48E1 adders in a 28-nm field-programmable-gate-array.

A field-programmable-gate-array (FPGA) based time-to-digital-converter (TDC), which combines different types of delay chains in a single time measurement channel, is reported in this paper. A new TDC architecture is developed, and both a carry-chain and the DSP48E1 adders, which are integrated inside the FPGA chip, are employed to achieve high resolution time tagging. A single channel TDC has a 3.3 ps averaged bin size, a 5.4 ps single-shot precision, and a maximum sampling rate of 250 MSa/s. The differential-non-linearity of the single TDC channel is -3.3 ps/+24.1 ps, and the integral-non-linearity is within -10.4 ps/+68.6 ps. The TDC performance can be improved by using four TDC channels to measure one input signal, and a 3.4 ps single-shot precision can be obtained. Due to the implementation of the delicated TDC structure, only a small amount of digital resources is required to achieve the picosecond time measurement resolution. Therefore, the reported TDC architecture is suitable for multi-channel applications that require high time resolution measurements of multiple input signals.

Implementation of 5.3 ps RMS precision and 350 M samples/second throughput time-to-digital converters with event sampling architecture in a Kintex-7 FPGA

Unlike the conventional field programmable gate array (FPGA) based time-to-digital converter (TDC) with clock sampling architecture, the TDC with event sampling architecture implemented in this paper propagates the system clock signal along the tapped-delay line (TDL) and the TDL status is sampled by a hit signal for time interpolation. Since there are several “1–0” and “0–1” transitions in the sampled TDL status, the TDC naturally realizes multiple measurements in parallel without increasing the resource consumption and the measurement dead time. Using a Xilinx Kintex-7 FPGA, we increase the number of equivalent TDC bins approximately to twice the number of physical delay cells in the TDL, which means the TDC resolution is about twice as good as the original. The average RMS precision is measured as 5.3 ps with two identical TDC channels measuring the time intervals in the range 0 to 20 ns. The proposed encoding scheme is so efficient that the TDC measurement throughput can reach 350 M samples per second. The test results show that the event sampling architecture is effective in FPGA as well. The performance that can be achieved is comparable with the performance of their counterparts that use the clock sampling architecture.

Design of a 32-channel NIM TDC module based on single FPGA for the μSR spectrometer prototype at the China Spallation Neutron Source

The design of an experimental muon source (EMuS) at the China Spallation Neutron Source (CSNS) has been underway for muon spin rotation, relaxation and resonance (μSR) experiments since 2007. A 128-channel μSR spectrometer prototype is also being developed. We have successfully developed a 32-channel time-to-digital converter (TDC) electronic readout unit module for the μSR spectrometer prototype. It receives timing signals from four front-end electronics (FEEs) and communicates with them. Moreover, it is a standard NIM module with a single field-programmable gate array-based design that meets the following requirements for μSR experiments: a low dead time, an instantaneous high count rate, a relatively long measurement duration, a relatively high resolution, and multiple channel-compatibility. By incorporating look-up tables (LUTs), placement constraints and area constraints, the routing skew of all TDC channels is reduced to less than 4 ps. Furthermore, Gigabit Ethernet data transmission has been incorporated in anticipation of more channels being added in the future.

A 6.6 ps RMS resolution time-to-digital converter using interleaved sampling method in a 28 nm FPGA.

Based on the adaptive logic module structure implemented in a 28 nm field programmable gate array (FPGA), we propose an interleaved sampling method, together with bin realignment operation, to enable time-to-digital converter (TDC) implementation. The tap status is sampled twice in a single physical channel, meaning that TDC precision beyond the cell delay limit can be anticipated. Two TDC channels were implemented in a 28 nm Cyclone-V FPGA, and the effectiveness of the proposed method was evaluated. After calibration, the TDC produced a timing resolution of 6.6 ps root mean square or 5.8 ps per least significant bit.

256 $\times$ TDC Array With Cyclic Interpolators Based on Calibration-Free $2{\times}$ Time Amplifier

This paper presents the design of a CMOS time-to-digital converter (TDC) used in a direct time-of-flight laser radar line receiver consisting of an array of single-photon avalanche diodes (SPADs) and 256 TDCs. The TDCs use the Nutt interpolation method, where the start/stop fine interpolators are based on a cyclic converter architecture. The cyclic converters use a delay-line-based time interval amplifier to double the quantization residue after each quantization cycle. The time amplifier, and the entire TDC array, does not need any biasing nor does the TDC results need any post-processing to provide sub-100-ps precision and uniformity across the TDC array, therefore making the design very robust and appealing for large designs where hundreds of TDCs are needed on a single chip. Fabricated in a 0.35μm CMOS technology, a single TDC channel occupies an area of 0.03 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and consumes a power of 1.17 mW @ 100 kHz measurement rate. The TDC has a measurement range of 640 ns, and with a resolution of 15 bits, the LSB is 20 ps. Linearity is ensured by the Nutt interpolation method while the rms single-shot precision of the TDC channel is 72 ps. Thus, when LIDAR applications are considered, the TDC is capable of providing a range of 96 m with a precision of 1 cm without any post-processing or calibration.

A 2.3-ps RMS Resolution Time-to-Digital Converter Implemented in a Low-Cost Cyclone V FPGA.

We present a nonuniform multiphase (NUMP) method to construct a high-resolution time-to-digital converter (TDC) for low-cost field-programmable gate array (FPGA) devices. The NUMP method involves a system clock being passed through a series of delay elements to generate multiple clocks with different phase shifts. The phases of the rising and falling edges of all the clocks are sorted in order and the states of all the clocks are latched when a hit signal arrives. The sizes of the time bins (and precision) of the NUMP method are not limited by the uniformity and minimum value of the time delays of the delay lines. In theory, any delay sources with small jitters in an FPGA, not just very fine carry chains, can be used in the NUMP method to delay and randomize the clocks. Thus, the NUMP method can achieve excellent TDC timing resolutions in low-cost FPGAs without very fine delay lines. We implemented four NUMP TDC channels in a low-cost FPGA device (an Altera Cyclone V 5CEBA4F23C7N). The performance of the four NUMP TDCs was evaluated using both internal and external pulses. The root mean square (rms) for the timing resolution measured using the internal and the external pulses with short-time intervals (less than 1 ns) was 2.3 and 5.2 ps, respectively. A 14.1-ps rms timing resolution was measured at a time interval of 517 ns. The NUMP method is suitable for applications that require a number of high-performance TDC channels in a low-cost FPGA.

A Multi-Chain Merged Tapped Delay Line for High Precision Time-to-Digital Converters in FPGAs

Field programmable gate array (FPGA)-based time-to-digital converters (TDCs) use a tapped delay line (TDL) for time interpolation to yield a sub-clock time resolution. The granularity and uniformity of delay cells in TDL determines achievable TDC time precision. To gain small delay cells in TDL, we propose a new TDL architecture by merging multiple conventional delay chains to obtain very fine intrinsic cell delays. The uniformity of these cell delays is improved by a bin decimation method so that the time interpolation with the TDL has minimum nonlinearity error. To evaluate the performance improvement using the new TDL architecture, two identical TDC channels with 1-chain, 2-chain, and 4-chain merged TDLs, respectively, were implemented in a Xilinx Kintex-7 FPGA. For time-intervals in the range from 0 to 50 ns, the average RMS precisions of these TDC pairs were measured as 8.5 ps, 5.3 ps, and 4.3 ps, respectively. The test results confirm that the proposed TDL architecture is an FPGA-independent effective method for boosting TDC precision without significant increase in hardware complexity and logic resource consumption.

A 1.15-ps Bin Size and 3.5-ps Single-Shot Precision Time-to-Digital Converter With On-Board Offset Correction in an FPGA

This paper presents the implementation of a high-resolution time-to-digital converter (TDC), which is adapted to varying environmental conditions. The TDC is implemented in field-programmable gate arrays (FPGA), using carry chains to achieve fine time measurement. Multiple carry chains are integrated in a single TDC channel for resolution enhancement. The TDC performance would suffer greatly without temperature compensation due to its sensitivity to the operating temperature. In order to improve the TDC adaptability, we analyzed the temperature-dependent delay variation function, and designed a powerful offset canceler to ensure stable performance of our TDC over a wide temperature range. The offset canceler can effectively correct the delay offset over temperature for the carry chain as well as for the signal transmission path. The TDC channels are tested to be fully functional with the operating temperature continuously varying from −20 °C to 60 °C. The averaged TDC bin size is 1.15 ps, and the single-shot precision is 3.5 ps. The duplications of the TDCs in three FPGA chips show good performance reproducibility according to the tests in a temperature chamber.

Toward Implementing Multichannels, Ring-Oscillator-Based, Vernier Time-to-Digital Converter in FPGAs: Key Design Points and Construction Method

For TOF positron emission tomography (TOF PET) detectors, time-to-digital converters (TDCs) are essential to resolve the coincidence time of the photon pairs. Recently, an efficient TDC structure called ring-oscillator-based (RO-based) Vernier TDC using carry chains was reported by our team. The method is very promising due to its low linearity error and low resource cost. However, the implementation complexity is rather high especially when moving to multi-channels TDC designs, since this method calls for a manual intervention to the initial fitting results of the compilation software. In this paper, we elaborate the key points toward implementing high performance multi-channels TDCs of this kind while keeping the least implementation complexity. Furthermore, we propose an efficient fine time interpolator construction method called the period difference recording which only needs at most 31 adjustment trials to obtain a targeted TDC resolution. To validate the techniques proposed in this paper, we built a 32-channels TDC on a Stratix III FPGA chip and fully evaluated its performance. Code density tests show that the obtained resolution results lie in the range of (23 ps ~ 37 ps), the differential nonlinearity (DNL) results lie in the range of (-0.4 LSB ~ 0.4 LSB) and the integral nonlinearity (INL) results lie in the range of (-0.7 LSB ~ 0.7 LSB) for each of the 32 TDC channels. This paper greatly eases the designing difficulty of the carry chain RO-based TDCs and can significantly propel their development in practical use.

A 0.65--1.35 GHz synthesizable all-digital phase locked loop with quantization noise suppressing time-to-digital converter

This paper presents a new quantization noise suppression method for a time-to-digital converter (TDC) and proposes an all-digital phase-locked loop (ADPLL) architecture using only standard cell logic gates. Using a new multiple input multiple output (MIMO) quantization noise suppression method provides an order of $\sqrt {2N} $ improvement in TDC resolution with $N$ parallel TDC channels. Suppressed noise in the TDC allows the ADPLL to achieve superior jitter performance in both theoretical calculations and simulation results. In order to allow fast portability between process nodes, short design cycle time, ease of modification, and flexibility, ADPLL architecture is designed completely in register transfer level intensive Verilog code and the implementation is synthesized in order to obtain final microelectronic design schematics. In comparison to similar work in the literature, postlayout simulation results show that the designed ADPLL achieves period jitter of 1.78 ps$_{rms}$ with a layout area of 0.09 mm$^{2}$ in 65 nm CMOS process and power consumption of 17.5 mW at 800 MHz.

A flexible 32-channel time-to-digital converter implemented in a Xilinx Zynq-7000 field programmable gate array

A high performance multi-channel time-to-digital converter (TDC) is implemented in a Xilinx Zynq-7000 field programmable gate array (FPGA). It can be flexibly configured as either 32 TDC channels with 9.9ps time-interval RMS precision, 16 TDC channels with 6.9ps RMS precision, or 8 TDC channels with 5.8ps RMS precision. All TDCs have a 380M Samples/second measurement throughput and a 2.63ns measurement dead time. The performance consistency and temperature dependence of TDC channels are also evaluated. Because Zynq-7000 FPGA family integrates a feature-rich dual-core ARM based processing system and 28nm Xilinx programmable logic in a single device, the realization of high performance TDCs on it will make the platform more widely used in time-measuring related applications.

A 3.9 ps Time-Interval RMS Precision Time-to-Digital Converter Using a Dual-Sampling Method in an UltraScale FPGA

Field programmable gate arrays (FPGAs) manufactured with more advanced processing technology have faster carry chains and smaller delay elements, which are favorable for the design of tapped delay line (TDL)-style time-to-digital converters (TDCs) in FPGA. However, new challenges are posed in using them to implement TDCs with a high time precision. In this paper, we propose a bin realignment method and a dual-sampling method for TDC implementation in a Xilinx UltraScale FPGA. The former realigns the disordered time delay taps so that the TDC precision can approach the limit of its delay granularity, while the latter doubles the number of taps in the delay line so that the TDC precision beyond the cell delay limitation can be expected. Two TDC channels were implemented in a Kintex UltraScale FPGA, and the effectiveness of the new methods was evaluated. For fixed time intervals in the range from 0 to 440 ns, the average RMS precision measured by the two TDC channels reaches 5.8 ps using the bin realignment, and it further improves to 3.9 ps by using the dual-sampling method. The time precision has a 5.6% variation in the measured temperature range. Every part of the TDC, including dual-sampling, encoding, and on-line calibration, could run at a 500 MHz clock frequency. The system measurement dead time is only 4 ns.

TOT measurement implemented in FPGA TDC**Supported by National Natural Science Foundation of China (11079003, 10979003)

Time measurement plays a crucial role for the purpose of particle identification in high energy physics experiments. With increasingly demanding physics goals and the development of electronics, modern time measurement systems need to meet the requirement of excellent resolution specification as well as high integrity. Based on Field Programmable Gate Arrays (FPGAs), FPGA time-to-digital converters (TDCs) have become one of the most mature and prominent time measurement methods in recent years. For correcting the time-walk effect caused by leading timing, a time-over-threshold (TOT) measurement should be added to the FPGA TDC. TOT can be obtained by measuring the interval between the signal leading and trailing edges. Unfortunately, a traditional TDC can recognize only one kind of signal edge, the leading or the trailing. Generally, to measure the interval, two TDC channels need to be used at the same time, one for leading, the other for trailing. However, this method unavoidably increases the amount of FPGA resources used and reduces the TDC's integrity.This paper presents one method of TOT measurement implemented in a Xilinx Virtex-5 FPGA. In this method, TOT measurement can be achieved using only one TDC input channel. The consumed resources and time resolution can both be guaranteed. Testing shows that this TDC can achieve resolution better than 15ps for leading edge measurement and 37 ps for TOT measurement. Furthermore, the TDC measurement dead time is about two clock cycles, which makes it good for applications with higher physics event rates.

Dual-Phase Tapped-Delay-Line Time-to-Digital Converter With On-the-Fly Calibration Implemented in 40 nm FPGA.

This paper describes two novel time-to-digital converter (TDC) architectures. The first is a dual-phase tapped-delay-line (TDL) TDC architecture that allows us to minimize the clock skew problem that causes the highly nonlinear characteristics of the TDC. The second is a pipelined on-the-fly calibration architecture that continuously compensates the nonlinearity and calibrates the fine times using the most up-to-date bin widths without additional dead time. The two architectures were combined and implemented in a single Virtex-6 device (ML605, Xilinx) for time interval measurement. The standard uncertainty for the time intervals from 0 to 20 ns was less than 12.83 ps-RMS (root mean square). The resolution (i.e., the least significant bit, LSB) of the TDC was approximately 10 ps at room temperature. The differential nonlinearity (DNL) values were [-1.0, 1.91] and [-1.0, 1.88] LSB and the integral nonlinearity (INL) values were [-2.20, 2.60] and [-1.63, 3.93] LSB for the two different TDLs that constitute one TDC channel. During temperature drift from 10 to 50(°)C, the TDC with on-the-fly calibration maintained the standard uncertainty of 11.03 ps-RMS.

A 20-ps Time-to-Digital Converter (TDC) Implemented in Field-Programmable Gate Array (FPGA) with Automatic Temperature Correction

This paper presents an automatic temperature correction design for carry chain based time-to-digital converter (TDC) in field-programmable gate array (FPGA). The bin-by-bin calibrations under different temperatures are performed for both plain TDC and Wave Union TDC to characterize the influence of temperature variation on the delay time of carry chain. Accordingly, a simplified temperature correction scheme by using a dedicated correction channel to measure the coefficient and correct fine time result for all TDC channels is implemented and tested. This method shows only few picosecond errors for both simulation and measurement. With this correction approach, a TDC precision of 21 ps has been achieved in Cyclone II FPGA under a wide ambient temperature range from 0 $^\circ{\rm C}$ to 60 $^\circ{\rm C}$ . Several design key points are also described in this paper.