Ring-Oscillator-Based High Accuracy Low Complexity Multichannel Time-to-Digital Converter Architecture for Field-Programmable Gate Arrays

Abstract

This article proposes and validates a low complexity multichannel ring-oscillator (RO)-based time-to-digital converter (TDC) architecture for field-programmable gate arrays (FPGAs). Channels of that TDC are mainly composed of look-up Tables (LUTs) configured as embedded memories. The channels share the same ring oscillator. A previously proposed delay tuning method was used to increase the overall accuracy by balancing the TDC channels. Compared to previously reported TDCs, the proposed architecture consumes fewer resources without degrading performances. A nine-channel TDC was implemented in a Zynq-7 Xilinx FPGA. Single-shot precision of 92.7 ps and accuracy of 92.9 ps were achieved, while consuming 1.49% and 1.31% of the available LUTs and FFs of a ZYNQxc7z010-3clg400 Xilinx FPGA, respectively.