A Multi-Chain Merged Tapped Delay Line for High Precision Time-to-Digital Converters in FPGAs

Abstract

Field programmable gate array (FPGA)-based time-to-digital converters (TDCs) use a tapped delay line (TDL) for time interpolation to yield a sub-clock time resolution. The granularity and uniformity of delay cells in TDL determines achievable TDC time precision. To gain small delay cells in TDL, we propose a new TDL architecture by merging multiple conventional delay chains to obtain very fine intrinsic cell delays. The uniformity of these cell delays is improved by a bin decimation method so that the time interpolation with the TDL has minimum nonlinearity error. To evaluate the performance improvement using the new TDL architecture, two identical TDC channels with 1-chain, 2-chain, and 4-chain merged TDLs, respectively, were implemented in a Xilinx Kintex-7 FPGA. For time-intervals in the range from 0 to 50 ns, the average RMS precisions of these TDC pairs were measured as 8.5 ps, 5.3 ps, and 4.3 ps, respectively. The test results confirm that the proposed TDL architecture is an FPGA-independent effective method for boosting TDC precision without significant increase in hardware complexity and logic resource consumption.