Time-domain Comparator Research Articles

A 0.5 V 10-bit SAR ADC with offset calibrated time-domain comparator

This paper presents a low voltage energy-efficient 10-bit SAR ADC. A double-merge and split (DMAS) switching scheme is proposed to reduce the CDAC switching energy by 92.2 % compared with conventional one without extra reference voltage (VCM). Gain tunable voltage-controlled delay unit (GT-VCDU) is proposed for offset calibration of time-domain comparator (TD-CMP). The residual offset is reduced by proposed stage-by-stage calibration. 1 sigma of TD-CMP offset is reduced to 0.8 mV. The SAR ADC is fabricated in the 55 nm CMOS process occupied a core area of 0.038mm2. With a supply voltage of 0.5 V and a Nyquist rate input, the prototype consumes 164 nW at 100kS/s. The ENOB is 8.86-bit, resulting a FoM of 3.53 fJ/conversion-step.

A Low-Offset VCO-Based Time-Domain Comparator Using a Phase Frequency Detector With Reduced Dead and Blind Zones

We present in this paper a high-precision voltage-controlled oscillators (VCO)-based time-domain (TD) comparator. It involves two identical and linear VCOs to convert the input voltage difference of the comparator into the time/frequency difference. Also, it includes a novel low-power phase frequency detector (PFD) to compare the output frequencies of the VCOs. The proposed PFD technique reduces the problematic effects of missing edges and phase ambiguity in conventional circuits by minimizing dead-zone (DZ)/blind-zone (BZ) and suppressing unwanted output glitches. The TD-comparator prototype is fabricated in a 350 -nm CMOS process having an active area of 0.01 mm2. The comparator consumes 93.65 μ W power from a 3.3 -V supply and provides a conversion rate of 2.7 MHz with 148 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\boldsymbol {\mu }\mathbf {V_{rms}}$ </tex-math></inline-formula> input-referred noise. Measurement results of 5 fabricated chips show an input-referred offset standard deviation of 81.14 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${\mu }\text{V}$ </tex-math></inline-formula> . Stand-alone characteristics measurements of the proposed PFD show a minimized DZ and BZ of less than 12 and 22.7 ps, respectively. With an almost <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${\pm 2\pi }$ </tex-math></inline-formula> input phase range, the maximum operating frequency of the PFD is 1.32 GHz.

Low-power bulk-driven time-domain comparator with high voltage-to-time gain for ADC applications

This paper, presents an ultra-low power time-domain comparator at low supplied voltages. In the proposed comparator structure, a novel delay element (DE) has been designed to produce a significantly high voltage-to-time gain, resulting in a high accuracy of the proposed comparator, saving of occupied area, and avoiding the extra power dissipation. The main idea of this work is to use the bulk terminal of a transistor as one of the comparator's inputs in the subthreshold region. The post-layout simulation results in 180 nm TSMC technology with a supply voltage of 1 V, show that the proposed comparator consumes about 250 nW, and the comparator's resolution is less than 0.4mv for 2.5 MHz clock frequency. Also, the Monte-Carlo analysis of the proposed time-domain comparator shows, the largest value of offset voltage is 2.8 mV. Finally, a 10-bit 0.5 V 91 kS/s monotonic SAR-ADC was designed and simulated using the proposed comparator. The power consumption of the ADC is 152 nW. The FoM of 2fJ/conversion-step proves the effectuality of the proposed comparator.

A 10-Bit 400-KS/s Low Noise Asynchronous SAR ADC with Dual-Domain Comparator for Input-Referred Noise Reduction.

This paper presents a low noise 0.6-V 400-kS/s asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) for input-referred noise reduction. A dual-domain comparator is proposed to optimize the power, noise, and sampling rate of the ADC in the 10-bit conversion. In order to optimize the figure of merits (FoM) of the ADC, the 10-bit conversion consists of a 7-bit coarse conversion with the double-tail dynamic comparator and a 3-bit fine conversion with the VCDL-based time-domain comparator. An asynchronous timing controller is also proposed to improve the ADC sampling rate and optimize the power consumption of the dual-domain comparator. The proposed SAR ADC is fabricated in 180-nm CMOS technology with an area of 0.836 mm2. At a 0.6-V supply voltage and a 400-kS/s sampling rate, the implemented SAR ADC achieves a signal-to-noise and distortion ratio (SNDR) of 56.59 dB and an effective number of bits (ENOB) of 9.16 bits. The peak values of DNL and INL are +0.47/−0.53 LSB and +0.92/−0.64 LSB, respectively. The FoM is 10.31 fJ/conversion step with a power consumption of 2.36 μW.

A 10-Bit 2.5-GS/s Two-Step ADC With Selective Time-Domain Quantization in 28-nm CMOS

In this paper, a single-channel two-step voltage-time hybrid domain analog-to-digital converter (ADC) is proposed. To achieve high sampling rate and high accuracy, 3.5-bit voltage domain MDAC and 7-bit high-speed time domain ADC (TD-ADC) are combined into a 10-bit hybrid ADC. In the first stage MDAC, a low-power push-pull amplifier is used to improve settling speed, and 1-bit redundancy is designed for calibration and dither injection. The TD-ADC with selective time domain quantization is implemented by a constant-current voltage to time converter (VTC) array and a direct positive feedback time domain comparator. The proposed VTC array can maintain high linearity with a large input swing in high-speed application. The prototype ADC was fabricated in a 28-nm CMOS process and occupied a core area of 0.074 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . Under a 0.95-V power supply, the chip achieves a measured peak SNDR of 53.2 dB and SFDR of 61.7 dB respectively at conversion rate up to 2.5 GS/s. The FOM is 48.2 fJ/conversion-step.

A 0.6-V 12-bit 13.2-fJ/conversion-step SAR ADC with time-domain VCDL-based comparator and metastability immunity technique

A 0.6-V 12-bit successive-approximation-register (SAR) analog-to-digital converter (ADC) is presented in this paper. Compared with the conventional time-domain comparator, the latch-like phase detector can reduce the dead zone voltage because of the positive feedback structure. Furthermore, a low power metastability immunity technique is proposed to suppress the uncertain decision-making behavior at the small input differences. The simulation results show that the proposed SAR ADC can achieve a 73.75-dB signal-to-noise and distortion ratio (SNDR) and consume 3.6 μW power consumption at the Nyquist input and sampling rate of 100 kS/s, resulting in a figure-of-merit (FOM) of 13.2 fJ/Conversion-step. Meanwhile, the core area is only 0.197 mm2 with the fully customized MOM capacitor array in a 0.18-μm CMOS process.

A 12-Bit 20-kS/s 640-nW SAR ADC With a VCDL-Based Open-Loop Time-Domain Comparator

This brief presents a 12-bit ultra-low-power asynchronous successive approximation register (SAR) analog-to-digital converter (ADC). A voltage-controlled delay line (VCDL) based open-loop time-domain comparator is proposed and analyzed, achieving low noise and ultra-low power performance. By employing the mixed switching scheme, the segmented capacitive digital-to-analog converter (CDAC) arrays as well as the synchronous data-weighted averaging (DWA) calibration block, the proposed SAR ADC can operate from 1.8 V down to 0.8 V at 20&#x2013;200 kS/s. The designed ADC is fabricated in a 0.18- <inline-formula> <tex-math notation="LaTeX">$\mu {\mathrm{ m}}$ </tex-math></inline-formula> CMOS process and the measurement results show the proposed SAR ADC achieves an SNDR of 65-dB with power consumption of 647 nW from a 0.8 V power supply at 20 kS/s.

A Time-Domain Comparator Based Skipping-Window SAR ADC

This paper presents an energy efficient successive-approximation register (SAR) analog-to-digital converter (ADC) for low-power applications. To improve the overall energy-efficiency, a skipping-window technique is used to bypass corresponding conversion steps when the input falls in a window indicated by a time-domain comparator, which can provide not only the polarity of the input, but also the amount information of the input. The time-domain comparator, which is based on the edge pursing principle, consists of delay cells, two NAND gates, two D-flip-flop register-based phase detectors and a counter. The digital characteristic of the comparator makes the design more flexible, and the comparator can achieve noise and power optimization automatically by simply adjusting the delay cell number. An energy efficient digital-to-analog converter (DAC) control scheme suitable for the skipping window technique is also developed to reduce the switching energy during SAR conversion. Together with the skipping-window technique, the linearity and the power consumption of the SAR ADC are improved. The impact of different window sizes on comparison cycles, DAC switching energy and the overall energy efficiency is analyzed. Simulation results show that the proposed skipping-window technique can improve the overall energy-efficiency of the SAR ADC, as well as the linearity, and the optimized window size for the overall energy efficiency will vary with the DAC switching energy.

Low power time-domain rail-to-rail comparator with a new delay element for ADC applications

In this paper, a rail-to-rail time-domain comparator with low power supply voltage and low power consumption is introduced. The comparator can be employed in low-power converters and biomedical applications. In the proposed time-domain comparator, a rail-to-rail delay element has been employed to generate a significant voltage-to-time gain for the full range of input signals. This circuit is designed, laid out, and simulated in 0.18 μm TSMC technology and powered by 0.6 V and 1 V supply voltages. The simulation results show that the proposed comparator has a rail-to-rail dynamic range and the power consumption of the circuit is 0.6 μW and 19 μW at the clock frequency of 10 MHz and 100 MHz, respectively. The active area of 56 μm × 14 μm shows the compactness of the circuit comparing to the other similar works. The proposed comparator was used in an ADC to show its effectiveness to improve the performance of the ADC. An 8-bit 0.8 V 100 kS/s SAR-ADC is designed and simulated. It consumes 430 nW and the figure of merit is 19.3fJ/conversion-step.

Offset-Calibration With Time-Domain Comparators Using Inversion-Mode Varactors

This brief presents a differential time-domain comparator formed by two voltage controlled delay lines, one per input terminal, and a binary phase detector for comparison solving. The propagation delay through the respective lines can be adjusted with a set of digitally controlled inversion-mode varactors. These varactors provide tuning capabilities to the comparator; feature which can be exploited for offset calibration. This is demonstrated with the implementation of a differential 10-bit successive approximation register analog-to-digital converters. The design, fabricated in a 0.18- $\mu \text{m}$ CMOS process, includes an automatic mechanism for adjusting the capacitance of the varactors in order to calibrate the offset of the whole converter. Correct functionality was measured in all samples.

A 0.5-V 12-bit SAR ADC Using Adaptive Time-Domain Comparator With Noise Optimization

This paper presents a 0.5-V 12-bit low-voltage power-efficient successive-approximation register (SAR) analog-to-digital converter (ADC) using an adaptive time-domain (ATD) comparator with noise optimization. To be power efficient with different residual input levels ( $\Delta V_{\mathrm {in}}$ ) during conversion, the proposed ATD comparator automatically adjusts its input-referred noise performance rather than consuming the same power for each bit conversion. Considering the noise requirement of 12-bit resolution, the proposed ATD technique effectively reduces the comparator power consumption by 50% compared to the conventional approach. Moreover, a differential threshold window (DTW) technique is also developed to provide the optimized time-domain threshold for lowest figure-of-merit (FoM) performance with a self-adjusted ( $V_{\mathrm {ctrlp}}$ – $V_{\mathrm {ctrln}}$ ), depending on process–voltage–temperature (PVT) variation. The test chip occupies a core area of 0.109 mm2 in Taiwan Semiconductor Manufacturing Company (TSMC) 90-nm CMOS technology. With a 0.5-V supply voltage, the prototype consumes 810 and 1425 nW at 100 and 250 kS/s, respectively. The achieved effective number of bits and signal-to-noise and distortion ratio with Nyquist-rate input are 10.71/10.3 bit and 66.3/63.8 dB, respectively. The resultant Walden FoM and Schreier FoM are 4.82/4.52 fJ/conversion step and 174.2/173.23 dB, respectively.

A High-Speed 2-bit/Cycle SAR ADC With Time-Domain Quantization

This brief presents a 2-bit/cycle successive approximation register (SAR) analog-to-digital converter (ADC) with time-domain quantization, which only needs one capacitive digital-to-analog converter (DAC) array. A duplicated dynamic comparator is adopted to generate the time references. To quantize the time value, a dynamic latch-based high precision time-domain comparator is proposed. Moreover, a redundancy technique is utilized to overcome the effect of nonideal factors, such as incomplete DAC settling, reference scale mismatch, and offset of comparators. A design example of 9-bit 700 MS/s SAR ADC in 65-nm CMOS technology is presented. Simulation results show that with a differential 600- ${\text {mV}}_{p-p}$ input, the spurious free dynamic range at Nyquist input is above 65 dB. The simulated effective number of bit is up to 8.3 bits at 10-MHz input with the presence of noise and mismatches calibration.

A 0.9 V 2.72 µW 200 kS/s SAR ADC with ladder-based time-domain comparator

A 0.9 V 2.72 µW 200 kS/s SAR ADC with ladder-based time-domain comparator

A 1-V 1.6-GS/s 5.58-ENOB CMOS Flash ADC using Time-Domain Comparator

A 1-V 1.6-GS/s 5.58-ENOB flash ADC with a high-speed time-domain comparator is proposed. The proposed time-domain comparator, which consumes low power, improves the comparison capability in high-speed operations and results in the removal of preamplifiers from the first-stage of the flash ADC. The time interpolation with two factors, implemented using the proposed time-domain comparator array and SR latch array, reduces the area and power consumption. The proposed flash ADC has been implemented using a 65-nm 1-poly 8- metal CMOS process with a 1-V supply voltage. The measured DNL and INL are 0.28 and 0.41 LSB, respectively. The SNDR is measured to be 35.37 dB at the Nyquist frequency. The FoM and chip area of the flash ADC are 0.38 pJ/c-s and 620 × 340 μm², respectively.

An Energy-Efficient Time-Domain Asynchronous 2 b/Step SAR ADC With a Hybrid R-2R/C-3C DAC Structure

This paper describes an energy-efficient SAR ADC for ultra-low power applications. The asynchronous 2 b/step scheme halves both conversion time and DAC/digital circuit's switching activities and hence likewise reduces static and dynamic energy consumption. A low-power sleep mode is engaged at the end of each clock period. The technical contributions of this work include: 1) an innovative 2 b/step reference scheme based on a hybrid R-2R/C-3C DAC to minimize DAC hardware, 2) an interpolation-assisted time-domain 2 b comparison scheme that saves 33% in comparator circuitry, and 3) a dual-edge-comparison mechanism that reduces the time-domain comparator's (TDC) switching activities by 50%. All these techniques help reduce circuit overhead and overall energy consumption. The prototype ADC was fabricated in 180 nm CMOS process with an active area of 0.103 mm 2 . With a single 0.6 V supply and reference, the ADC achieves an ENoB of 9.2 bits and a FoM of 6.7 fJ/conversion-step while sampling at 100-kS/s.

A 100-kS/s 8.3-ENOB 1.7-&lt;named-content content-type="math" xlink:type="simple"&gt; &lt;inline-formula&gt; &lt;tex-math notation="TeX"&gt;$\mu\hbox{W}$&lt;/tex-math&gt;&lt;/inline-formula&gt;&lt;/named-content&gt; Time-Domain Analog-to-Digital Converter

A 100-kS/s time-domain analog-to-digital converter (TDADC) with successive approximation register architecture provides 8.3 effective bits. The time-domain comparator of the TDADC is realized with only one delay line consisting of a digitally controlled delay line and a voltage-controlled delay line. Therefore, the linearity degradation due to the mismatch between multiple delay lines can be avoided. The TDADC has been implemented in a 0.11- $\mu\hbox{m}$ CMOS process with a 0.127- $\hbox{mm}^{2}$ active silicon area. The TDADC consumes 1.7 $\mu\hbox{W}$ from a 0.6-V supply voltage.

A 1.0-V 6-b 40 MS/s time-domain flash ADC in 0.18 μm CMOS

This paper presents a 6-bit low power low supply voltage time-domain comparator. The conventional voltage comparison is moved to time-domain so as to remove pre-amplifier and latch, which enables its feasibility to low supply voltage. The voltage-to-time converter is realized by the proposed linear pulse-width-modulation. The set-up time of the D flip-flop determines the sampling rate of the converter. The resistive averaging relaxes the matching requirement of the parallel comparison cells. The total input capacitance is decreased to less than 40fF in this architecture. The above digital-intensive setting makes the analog-to-digital converter (ADC) benefit from technology scaling in both power consumption and sampling rate. The prototype ADC is fabricated in SMIC 0.18 μm CMOS process. At 40 MS/s and 1.0-V supply, it consumes 540 μW and achieves an effective-number-of-bit of 5.43, resulting in a figure-of-merit of 0.31 pJ/conversion-step and active area of 0.1 mm2.

A high SFDR 6-bit 20-MS/s SAR ADC based on time-domain comparator

This paper presents a 6-bit 20-MS/s high spurious-free dynamic range (SFDR) and low power successive approximation register analog to digital converter (SAR ADC) for the radio-frequency (RF) transceiver front-end, especially for wireless sensor network (WSN) applications. This ADC adopts the modified common-centroid symmetry layout and the successive approximation register reset circuit to improve the linearity and dynamic range. Prototyped in a 0.18-μm 1P6M CMOS technology, the ADC performs a peak SFDR of 55.32 dB and effective number of bits (ENOB) of 5.1 bit for 10 MS/s. At the sample rate of 20 MS/s and the Nyquist input frequency, the 47.39-dB SFDR and 4.6-ENOB are achieved. The differential nonlinearity (DNL) is less than 0.83 LSB and the integral nonlinearity (INL) is less than 0.82 LSB. The experimental results indicate that this SAR ADC consumes a total of 522 μW power and occupies 0.98 mm2.

Design of 12 bit Successive Approximation Analog-to-Digital Converter

In this paper, a 12 bit Successive Approximation Analog to Digital Converter has been designed which has high resolution, less power consumption and medium speed. The circuit has been designed and simulated on Cadence tool in 0.35μm AMS technology with a supply voltage of 3.3V. Different ADC architectures are present but this SAR ADC has a salient feature of providing high resolution with increased accuracy. In this all the building blocks of SAR ADC have been designed such that they meet the desired specifications. The time domain comparator is used such as to obtain low power consumption. The layout of all the blocks has been done on Cadence Virtuoso and process corner analysis is also done to meet the desired specifications. General Terms Comparator, Phase Detector, Switch Circuit for DAC

분할-커패시터 기반의 차동 디지털-아날로그 변환기를 가진 10-bit 10-MS/s 0.18-㎛ CMOS 비동기 축차근사형 아날로그-디지털 변환기

This paper describes a 10-bit 10-MS/s asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) using a split-capacitor-based differential digital-to-analog converter (DAC). SAR logic and comparator are asynchronously operated to increase the sampling frequency. The time-domain comparator with an offset calibration technique is used to achieve a high resolution. The proposed 10-bit 10-MS/s asynchronous SAR ADC with the area of is fabricated using a 0.18- CMOS process. Its power consumption is 1.19 mW at 1.8 V supply. The measured SNDR is 49.95 dB for the analog input frequency of 101 kHz. The DNL and INL are +0.57/-0.67 and +1.73/-1.58, respectively.