An Energy-Efficient Time-Domain Asynchronous 2 b/Step SAR ADC With a Hybrid R-2R/C-3C DAC Structure

Abstract

This paper describes an energy-efficient SAR ADC for ultra-low power applications. The asynchronous 2 b/step scheme halves both conversion time and DAC/digital circuit's switching activities and hence likewise reduces static and dynamic energy consumption. A low-power sleep mode is engaged at the end of each clock period. The technical contributions of this work include: 1) an innovative 2 b/step reference scheme based on a hybrid R-2R/C-3C DAC to minimize DAC hardware, 2) an interpolation-assisted time-domain 2 b comparison scheme that saves 33% in comparator circuitry, and 3) a dual-edge-comparison mechanism that reduces the time-domain comparator's (TDC) switching activities by 50%. All these techniques help reduce circuit overhead and overall energy consumption. The prototype ADC was fabricated in 180 nm CMOS process with an active area of 0.103 mm 2 . With a single 0.6 V supply and reference, the ADC achieves an ENoB of 9.2 bits and a FoM of 6.7 fJ/conversion-step while sampling at 100-kS/s.