Time-dependent Dielectric Breakdown Reliability Research Articles

Breakdown voltage and TDDB performance improvement by optimizing the PECVD dielectric film characteristics in MIM capacitors

The dielectric breakdown voltage (BV) and time dependent dielectric breakdown (TDDB) are the most important concerns for device reliability. In this study, the silicon nitride (SiNx) used as metal-insulator-metal (MIM) capacitor dielectric was successfully prepared by a dual-frequency plasma enhanced chemical vapor deposition (PECVD) method. Fourier transform infrared (FTIR) absorption spectra and electrical characterization results suggest that the SiNx film possesses higher dielectric breakdown voltage performance by decreasing SiH4/NH3 gas flow ratio or optimizing the interface layer among multiple layers. Similarly, the TDDB reliability test based on Weibull distribution indicates an increase in failure lifetime of the MIM capacitors by adjusting RF power and NH3 gas flow.

Reliability Analysis on TiN Gated NMOS Transistors

Compared to poly Si gate, metal gate has no gate depletions and experiences inversion capacitance gain, which makes an advantage for devices scaling. In this paper, we investigated the gate oxide leakage current and Time Dependent Dielectric Breakdown (TDDB) characteristics of TiN and poly Si electrodes with a 3.5 to 5 nm SiO2 dielectric thickness range. According to the Transmission Electron Microscope (TEM) analysis there is difference in oxide thickness. The SiO2 thickness of TiN gate electrode has been reduced by ~0.25 nm, considerably because of a scavenging effect. We normalized the reduced SiO2 thickness with an electrical oxide field, and there were no differences between the two electrodes in gate leakage current, accumulation breakdown voltage (BV), and accumulation TDDB lifetime. Therefore, we found the scavenging effect of TiN electrodes seems to affect little the leakage current and TDDB reliability of SiO2 dielectric. On the other hand, the BV and TDDB lifetime of TiN electrode in the inversion region are little bit better than that of the poly electrode. We think this differences are originated from the difference between TiN/SiO2 and poly Si/SiO2 interfaces.

Improved TDDB Reliability and Interface States in 5-nm Hf0.5Zr0.5O2 Ferroelectric Technologies Using NH3 Plasma and Microwave Annealing

This article reports that the enhanced forward gate bias time-dependent dielectric breakdown (TDDB) reliability and interface quality are achieved in 5-nm ferroelectric Hf0.5Zr0.5O2 (HZO) technologies by using the NH3 plasma interfacial layer (IL) treatment and microwave annealing (MWA). An orthorhombic crystalline phase is observed in the annealed HZO film with NH3 plasma IL treatment and MWA, and NH3 plasma IL treatment can suppress Hf/Zr interdiffusion. Metal-oxide-semiconductor capacitors (MOSCAPs) subjected to NH3 plasma IL treatment and 2100-W MWA also have a higher extrapolated operating voltage for a ten-year lifetime at 0.01% failure and lower interface state density ( ${D}_{\textit {it}}$ ) compared to the devices subjected to only rapid thermal annealing (RTA) at 600 °C. Therefore, NH3 plasma treatment and MWA are effective for improving the TDDB reliability and interface quality of the ultrathin ferroelectric HZO.

Liner- and barrier-free NiAl metallization: A perspective from TDDB reliability and interface status

This study reports the time-dependent-dielectric-breakdown (TDDB) reliability of NiAl on SiO2 without any barrier layer. NiAl was indicated to exhibit superior TDDB reliability in comparison to Cu/TaN in the time-to-failure (4200 s versus 240 s, at 4 MV/cm at 200 °C) and in the breakdown activation energy under 4 MV/cm (1.17 eV versus 0.87 eV). Moreover, NiAl was found to form an atomically thin and self-limiting Al oxide layer at the NiAl/SiO2 interface, and this Al oxide layer, together with the large cohesive energy of NiAl, was considered to be possible origin for the excellent reliability. The results demonstrate a great potential of NiAl as a liner- and barrier-free interconnect material.

Front-end of line and middle-of-line time-dependent dielectric breakdown reliability simulator for logic circuits

This paper presents a methodology for lifetime estimation of Front-End-of-Line (FEOL) and Middle-of-Line (MOL) time dependent dielectric breakdown (TDDB) in state-of-art logic circuits. The algorithm to extract vulnerable features of MOL-TDDB has been developed and implemented. A traditional 8-bit FFT circuit and a state-of-art Leon3 microprocessor are considered for lifetime calculation. The impact of different use scenarios on circuits is also investigated.

Experimental study of time-dependent dielectric breakdown in tri-gate nanowire transistor

We systematically investigate the size dependence of the time-dependent dielectric breakdown (TDDB) in a tri-gate nanowire transistor (NW Tr.). It is newly found that TDDB reliability is degraded in NW Tr. as compared with that in a planar transistor owing to the locally enhanced electric field at the NW corner. Moreover, in the region with a width (W) less than 40 nm, nanowire width reduction leads to a shorter time to gate dielectric breakdown indicating additional degradation of TDDB reliability in NW Tr. with smaller W. Although TDDB in three-dimensional (3D) MOS structures such as a trench MOS capacitor has already been reported, the size dependence of TDDB in scaled NW Tr. is firstly discussed in this paper since a trench capacitor is different from recent NW Tr. in structure, device size, gate dielectric thickness, and scaling effect on TDDB.

Reliability tests of electroless barriers against copper diffusion under bias-temperature stress with n- and p-type substrates

To investigate the similarity and difference of substrate conduction type in the time-dependent dielectric breakdown (TDDB) tests for the barrier integrity against Cu diffusion under bias-temperature stress (BTS), the TDDB reliability of electroless NiB and CoWP/NiB was determined by metal oxide semiconductor (MOS) structures on n-type Si (n-Si) substrates, and the test results were compared with those using p-type Si (p-Si) substrates. The TDDB results and mechanism were observed to be qualitatively the same as Cu diffusion for both conduction types. However, the TDDB lifetime using p-Si was found to be potentially shorter because of the reverse bias conditions than that using n-Si under the forward bias conditions.

ALD TaN Barrier for Enhanced Performance with Low Contact Resistance for 14nm Technology Node Cu Interconnects

We report on an alternative, atomic layer deposited (ALD) TaN barrier scheme for Cu interconnects for 14nm technology node and beyond, i.e., 64nm pitch and/or smaller interconnects. With VLSI integration requiring denser packing of interconnects, conformal fill of progressively narrower trenches and vias with high aspect ratio, presents tough challenge for line-of-sight physical vapor deposition processes. ALD overcomes these gap-fill challenges but has disadvantages of low throughput, chemical residues and relatively lower density of ALD barriers for effective blocking of O2and Cu diffusion. From gap-fill perspective, ALD films enable ultrathin, conformal barrier with reduced problems of overhang and large bottom thickness, typical of physical vapor deposited (PVD) films. Reduced bottom-thickness enables via-contact resistance reduction and less overhang improves gap-fill, while maximizing Cu volume in a trench/via structure. Our blanket film studies show that ALD films are 10-15% less dense compared to Ta-rich PVD films, and more importantly only desired low-resistance alpha-Ta nucleates on ALD films vs. thin PVD films. The conformality of ALD TaN as well as the nucleation of alpha-Ta on it form the basis of via contact resistance reduction, leading to performance enhancement.A plasma-enhanced ALD (PEALD) process helps increase density and improves the hermeticity of the barrier. But PEALD can cause dielectric damage and lead to TDDB failures especially in smaller technology nodes. To maximize density while protecting low-k dielectric during deposition and maintaining low-contact resistance, we explored different flavors and combinations of thermal (tALD) and plasma-enhanced ALD (PEALD). In this work, we use a new, commercially available 40 MHz direct-plasma ALD tool and corresponding optimized processes to maximize throughput and minimize dielectric damage. Different ALD flavors, viz., tALD+post plasma(PP) treatment, tALD/PEALD bilayer films were evaluated for 14 nm technology groundrule interconnects in k=2.7 and k=2.55 dielectric levels. We were able to achieve via contact resistance reduction of 25-35%, with equivalent or better performance for yield, defectivity and electromigration (EM), time-dependent dielectric breakdown (TDDB) and stress migration (SM) reliability. In-line measured defect density for dual-damascene interconnects in k=2.55 dielectric was studied with a conservative ALD TaN thickness process window; the splits with 15-20A of tALDPP TaN barrier layers were found to have the lowest defectivity. Similar data for various ALD splits vs. PVD showed that the same tALDPP process with a certain thickness combination of the bilayer TaN/ Ta resulted in least defect density. This same optimized condition looked best for viachain yield for a macro with ~108via links at 14nm groundrule. We also confirmed that the same condition resulted in the lowest via contact resistance for fully landed vias for 45 chiplets across 3 wafers; where via bottom size variation was <10%. Another study with several bilayer ALD splits in k=2.55 dielectric, showed that the 5tALD/5PEALD condition with initial tALD layer protecting the low-k dielectric followed by denser PEALD to get a more effective barrier, yielded better than PVD TaN. The lowest via resistance data was also recorded for the same split. The EM stress results for both via and line-depletion at each of k=2.7 and k=2.55 levels were also studied. ALD splits were slightly worse than PVD condition with the exception of one stress direction, but still pass reliability targets scaled from the 22 nm technology node. The kinetics data for via depletion tests results in activation energy in excess of 1 eV. TDDB stress results were obtained for builds in both k=2.7 and k=2.55 dielectrics. The most significant impact of ALD on TDDB was the restoration of voltage acceleration parameter (gamma) for both levels. Gammas (slopes of lines) for ALD of all three devices were clearly higher. This confirmed that our optimized ALD condition does no damage to the dielectric. Lastly, impact of different liner processes on stress migration (SM) was investigated at 225oC stress for 1000 hours. There were no stress fails on any of the liner splits from the traditional plate and nose type SM structures. In summary, ALD TaN is shown to be a robust alternative barrier for Cu interconnect technology for technologies nodes like 14nm and smaller. The process can be optimized to give ~30% reduction in via contact reduction while preserving healthy yield, defect density and EM, TDDB and SM reliability.

As-grown donor-like traps in low-k dielectrics and their impact on intrinsic TDDB reliability

Highly porous low-k dielectrics are essential for downscaling of the interconnects for 20–10nm technologies. A planar capacitor test vehicle was used to investigate the intrinsic time dependent dielectric breakdown (TDDB) reliability of low-k dielectrics and the origin of an observed C–V hysteresis was studied. We hypothesize that the hysteresis is caused by donor-like traps present in the bulk of the low-k but not by electron/hole trapping or mobile charges. It is proposed that porogen/carbon residues are the source of these donor-like traps. Using Ileak vs. time measurements, it was found that the donor-like traps accelerate the dielectric degradation due to an enhanced EOX, causing a localized partial breakdown. The intrinsic TDDB reliability of the low-k film was improved by adding a sealing layer as such layer blocked the donor-like traps discharging.

Time-dependent dielectric breakdown in pure and lightly Al-doped Ta2O5 stacks

The time-dependent dielectric breakdown (TDDB) characteristics of 7 nm pure and lightly Al-doped Ta2O5 (equivalent oxide thickness of 2.2 and 1.5 nm, respectively) with W gate electrodes in MOS capacitor configuration are studied using gate injection and constant voltage stress. The effect of both the process-induced defects and the dopant on the breakdown distribution, and on the extracted Weibull slope values, are discussed. The pre-existing traps which provoke weak spots dictate early breakdowns. Their effect is compounded of both the stress-induced new traps generation (percolation model is valid) and the inevitable lower-k interface layer in the region with long time-to-breakdown. The domination of one of these competitive effects defines the mechanism of degradation: the trapping at pre-existing traps appears to dominate in Ta2O5; Al doping reduces defects in Ta2O5, the generation of new traps prevails over the charge trapping in the doped samples, and the mechanism of breakdown is more adequate to the percolation concept. The doping of high-k Ta2O5 even with small amount (5 at.%) may serve as an engineering solution for improving its TDDB characteristics and reliability.

Time-Dependent Dielectric Breakdown on Subnanometer EOT nMOS FinFETs

In this paper, the time-dependent dielectric breakdown (TDDB) in sub-1-nm equivalent oxide thickness (EOT) n-type bulk FinFETs is studied. The gate stacks consist of an IMEC clean interfacial layer, atomic layer deposition HfO2 high-k and TiN metal electrode. For the 0.8-nm EOT FinFETs, it is found that TDDB lifetime is consistent with results of planar devices for areas around , implying that the FinFET architecture does not seem to introduce new failure mechanisms. However, for devices with smaller area, the extrapolated voltage at a ten-year lifetime for soft breakdown (SBD) does not meet the specifications, and as a consequence, the SBD path wear-out will have to be included in the final extrapolation. Furthermore, it is shown that for EOTs smaller than 0.8 nm, the TDDB reliability on n-type FinFETs is challenged by the high leakage currents.

Electrical Characteristics and Temperature Response of Al2O3 Gate Dielectrics with and without Nitric Acid Compensation

In this paper, the Al2O3 gate dielectrics prepared by the in situ oxidation of sputtered Al in Ar/O2 ambient at room temperature and then without and with HNO3 compensation are demonstrated. It was found that the saturation substrate injection currents of MOS capacitors with P-type Si substrate at the positive bias region exhibit perimeter-dependent characteristics due to the enhanced fringing field effect. The temperature responses of perimeter-dependent saturated currents are different between two samples. The sample with HNO3 compensation shows regular dependence of substrate current on ni, but the one without HNO3 compensation exhibits additional current components come from oxide nonuniformity and interface trap density. The gate leakage current density at the negative bias region and the time-dependent dielectric breakdown reliability at 25 oC and 125 oC of Al2O3 capacitors can be improved by utilizing HNO3 compensation. It is believed that the HNO3 compensation is beneficial to the improvement of the SiO2/Si interface and the quality of the Al2O3/SiO2 oxide stacks.

Influence of the UV Cure on Advanced Plasma Enhanced Chemical Vapour Deposition Low-kMaterials

In a recent study, low-k thin films with low dielectric constant (≤2.1) and high Young's modulus (>5 GPa) were obtained by introducing a remote plasma step between the traditional plasma enhanced chemical vapour deposition and UV curing. This study shows that the UV curing step with a narrow band lamp with wavelength of 172 nm induced more network Si–O and Si–H bonds and more densification than the curing step with a broadband lamp with wavelengths higher than 200 nm. As a consequence, the dielectric constant of the narrow band cured film was slightly higher, but Young's modulus and hardness were much improved. Electrical characterization showed good breakdown voltages and a more than sufficient time dependent dielectric breakdown reliability. The broadband lamp was then used to form thicker films which retained very well the characteristics of the thin films.

Influence of the UV Cure on Advanced Plasma Enhanced Chemical Vapour Deposition Low-k Materials

In a recent study, low-k thin films with low dielectric constant (≤2.1) and high Young's modulus (>5 GPa) were obtained by introducing a remote plasma step between the traditional plasma enhanced chemical vapour deposition and UV curing. This study shows that the UV curing step with a narrow band lamp with wavelength of 172 nm induced more network Si–O and Si–H bonds and more densification than the curing step with a broadband lamp with wavelengths higher than 200 nm. As a consequence, the dielectric constant of the narrow band cured film was slightly higher, but Young's modulus and hardness were much improved. Electrical characterization showed good breakdown voltages and a more than sufficient time dependent dielectric breakdown reliability. The broadband lamp was then used to form thicker films which retained very well the characteristics of the thin films.

Addressing Cu/Low-$k$ Dielectric TDDB-Reliability Challenges for Advanced CMOS Technologies

Low- <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</i> dielectrics, which are beneficial for chip resistance-capacitance ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">RC</i> ) delay improvement, crosstalk-noise minimization, and power-dissipation reduction, are indispensable for the continuous scaling of advanced VLSI circuits, particularly that of high-performance logic circuits. In this paper, several critical challenges for Cu/low- <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</i> time-dependent dielectric-breakdown (TDDB)-reliability qualification will be reviewed. First, a low- <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</i> TDDB field-acceleration model and its determination will be discussed. Second, the macroscopic interconnect line-to-line spacing variation across the wafer and the microscopic line-to-line spacing nonuniformity induced by line-edge roughness within the same test structure and their impacts on low- <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</i> TDDB reliability will be carefully examined. The Weibull shape-parameter dependence on applied stress voltage due to such global and local spacing variations will be analyzed. Finally, the moisture effect on low- <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</i> TDDB and capacitance stability as an example of the impact from process integration will be reported, demonstrating that low- <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</i> TDDB is sensitive to back-end-of-the-line integration.

Physical Understanding of Strain-Induced Modulation of Gate Oxide Reliability in MOSFETs

We have systematically investigated the effects of strain on the gate oxide reliability, using biaxially strained Si MOSFETs, to elucidate their physical origins. It was found that the time-dependent dielectric breakdown reliability was significantly improved in strained Si nMOSFETs but was slightly degraded in strained Si pMOSFETs. These observations could be well explained by the strain-induced modulation of the gate current, resulting from band-structure modulation in the channels. It was also found that negative bias temperature instability was degraded in the strained Si pMOSFETs. This fact was attributable to the strain-induced enhancement of hole tunneling probability and hole wave function penetration into Si-H bonding states near the MOS interface, which could enhance Si-H bond breaking.

Cu/low- k dielectric TDDB reliability issues for advanced CMOS technologies

With the wide application of low- k and ultra-low- k dielectric materials at the 90 nm technology node and beyond, the long-term reliability of such materials is rapidly becoming a critical challenge for technology qualification. Low- k time-dependent dielectric breakdown (TDDB) is usually considered as one of the most important reliability issues during Cu/low- k technology development because low- k materials generally have weaker intrinsic breakdown strength than traditional SiO 2 dielectrics. This problem is further exacerbated by the aggressive shrinking of the interconnect pitch size due to continuous technology scaling. In this paper, three critical issues of low- k TDDB characteristics during low- k development and qualification will be reviewed. In the first part, a low- k TDDB field acceleration model and its determination will be discussed. In the second part, low- k dielectric time-to-breakdown ( t BD) statistical distribution and TDDB area scaling law for reliability projection will be examined. In the last part, as low- k TDDB has been found to be sensitive to all aspects of integration, the effects of process variations on low- k TDDB degradation will be demonstrated. Some key aspects which need to be carefully addressed to control overall low- k TDDB performance from process and integration side will be discussed.

Electrical conduction and TDDB reliability characterization for low- k SiCO dielectric in Cu interconnects

Leakage current and conduction mechanism of low-dielectric constant (low- k) carbon-doped silicon oxide (SiCO) for back-end-of-line (BEOL) dielectric are investigated in this work. Temperature-dependent leakage, Schottky emission and Poole–Frenkel emission for dense and porous low- k SiCO are analyzed respectively. Furthermore, time-dependent dielectric breakdown (TDDB) study at low electrical field verifies a square root of electrical field behaviour for low- k SiCO lifetime prediction. Besides, TDDB with regard to lifetime distribution, failure mode, thermal activation energy, and length scaling effect are also investigated. Finally, TDDB characterization of dense and porous low- k SiCO is carried out for the reference of process improvement and risk assessment.

Influence of CMP Slurries and Post-CMP Cleaning Solutions on Cu Interconnects and TDDB Reliability

We investigated Cu/low-k integration to test the time-dependent dielectric breakdown (TDDB) reliability of Cu interconnects. We described the relationship between TDDB lifetime and defects possibly caused by the Cu chemical-mechanical polishing (CMP) process, such as rough copper surface corrosion, crevice corrosion, and scratches, using Cu/silicon oxycarbide interconnects. Although rough copper surface corrosion has an insignificant effect on the TDDB lifetime, crevice corrosion at the edges of wires does cause TDDB degradation. We also found that a structure’s TDDB lifetime was affected by the kind of post-CMP cleaning solutions used when barrier metal slurries do not contain benzotriazole (BTA). These results indicate that two types of processes for post-CMP cleaning should be used. It is best to use solutions that do not have strong oxidized copper dissolution ability but can remove particles when a barrier metal slurry with an inhibitor other than BTA is used. Also good are solutions with a strong oxidized copper dissolution ability that have been optimized to prevent Cu corrosion when a barrier metal slurry with BTA is used. To improve TDDB reliability, care must be taken with regard to the combination of the barrier metal slurry and the post-CMP cleaning solution.

Analysis of Post-Chemical-Mechanical-Polishing Cleaning Mechanisms for Improving Time-Dependent Dielectric Breakdown Reliability

Using interconnects, we investigated the relationship between the time-dependent dielectric breakdown (TDDB) reliability and the cleaning process in copper chemical-mechanical polishing (CMP). We found that the formation of a nonuniform copper oxide film during post-CMP cleaning causes TDDB degradation when a barrier metal slurry that does not contain benzotriazole is used. We also found the reformation of a nonuniform copper oxide layer that accompanies the deionized water rinse is due to the dissolution of too much of the copper oxide film during the post-CMP cleaning process. For improved TDDB reliability, the uniform copper oxidization during the post-CMP cleaning process is important in the damascene integration process.