Time-dependent Dielectric Breakdown Reliability Research Articles

Nondestructive electrical characterization of integrated interconnect line-to-line spacing for advanced semiconductor chips

Poor process controls may cause huge line spacing variation across a semiconductor wafer during back-end-of-the-line integration in advanced semiconductor integrated circuit fabrication. As a consequence, significant degradation in yield, performance, and reliability may be observed. Line spacing variation also imposes challenges for accurate time dependent dielectric breakdown reliability lifetime projection. In this paper, a nondestructive, fast electrical method for determining a line-to-line spacing of a semiconductor chip is proposed. The method includes experimentally determining a slope from capacitance measurement (kCA), experimentally determining a slope from current-voltage measurement (kSE), and finally determining a line-to-line spacing from the slope kCA and the slope kSE. The line-to-line spacing determined from this method shows an excellent agreement with constructional analysis data.

Effects of carbon residue in atomic layer deposited HfO2 films on their time-dependent dielectric breakdown reliability

The effect of the carbon residue on the reliability of HfO2 thin films was investigated. HfO2 films were deposited on Si wafers by atomic layer deposition at a wafer temperature of 250°C using Hf[N(CH3)2]4 and O3 oxidant with two different densities (160 and 390g∕m3). The films deposited at the higher O3 density contained a lower concentration of carbon impurities. The leakage current density was lower and the time-dependent dielectric breakdown was improved in the higher O3 density films. First principles calculations confirmed that trap sites were generated in the band gap of HfO2 when carbon was interstitially or substitutionally present.

Impact of Crystalline Phase of Ni-FUSI Gate Electrode on Bias Temperature Instability and Gate Dielectric Breakdown of HfSiON MOSFETs

We investigated the influences of gate metals (n+/p+ poly-Si, Ni silicide (NiSi), Ni3Si) on the time dependent dielectric breakdown (TDDB) reliability and negative/positive bias temperature instability (NBTI/PBTI) of phase-controlled Ni-full-silicide (Ni-FUSI)/HfSiON/SiO 2 FETs. The TDDB reliability of NiSi-electrode n-FETs was comparable to that of n+-poly-Si-electrode n-FETs. However, further Ni enriching of the electrode to Ni3Si degraded the reliability. A degradation of the base SiO2 layer seems to have been responsible for this. A higher compressive strain was observed for the Ni3Si sample, which may have caused the degradation of the bottom SiO2. In contrast, the TDDB reliability of p-FETs improved much by using Ni3Si. We attribute this improvement to the lower cathode energy and/or the absence of boron in the gate electrode. The PBTI of the n-FETs was negligible and was not degraded by Ni enrichment of the gate electrode and additional annealing, suggesting that HfSiON was stable against the Ni-FUSI process. The threshold voltage (VT) shift in NBTI of p-FETs did not depend much on the gate materials. The major component of the V T shift in NBTI, however, was changed by Ni enriching from the generation of interface traps to the trapping of holes by the HfSiON bulk

Robust porous SiOCH/Cu interconnects with ultrathin sidewall protection liners

Robust porous low-k/Cu interconnects have been developed for 65-nm-node ultralarge-scale integrations (ULSIs) with 180-nm/200-nm pitched lines and 100-nm diameter vias in a single damascene architecture. A porous plasma-enhanced chemical vapor deposition (PECVD)-SiOCH film (k=2.6) with subnanometer pores is introduced into the intermetal dielectrics on the interlayer dielectrics of a rigid PECVD-SiOCH film (k=2.9). This porous-on-rigid hybrid SiOCH structure achieves a 35% reduction in interline capacitance per grid in the 65-nm-node interconnect compared to that in a 90-nm-node interconnect with a fully rigid SiOCH. A via resistance of 9.7 /spl Omega/ was obtained in 100-nm diameter vias. Interconnect reliability, such as electromigration, and stress-induced voiding were retained with interface modification technologies. One of the key breakthroughs was a special liner technique to maintain dielectric reliability between the narrow-pitched lines. The porous surface on the trench-etched sidewall was covered with an ultrathin plasma-polymerized benzocyclobuten liner (k=2.7), thus enhancing interline time-dependent dielectric breakdown reliability. The introduction of a porous material and the control of the sidewall are essential for 65-nm-node and beyond scaled-down ULSIs to ensure high levels of reliability.

Influence of Post-CMP Cleaning on Cu Interconnects and TDDB Reliability

The etching amount of Cu wires produced by post-chemical-mechanical polishing cleaning was studied. By using polyvinyl alcohol brush cleaning, the cleaning strength concentrates on the center chip of the wafer, which leads to the erosion of Cu interconnects. The etching depths of isolated Cu wires and dense Cu wires were compared. The surface on the isolated Cu wires is etched deeply because of the nonliner diffusion of the solution and the difference between the friction strengths of both wire patterns. These etching depths were improved by optimizing the brush formation, the rotation speed of the roller and the brush, and by using organic-acids. With respect to the dependence of time-dependent dielectric breakdown (TDDB) lifetime on waiting time, there is a difference between the diluted hydrofluoric-acid (DHF) and organic-acid solutions. The TDDB lifetime for the DHF cleaning is similar until after a waiting time of ten days, whereas the TDDB lifetimes for organic-acids are similar until after a waiting time of four days.

Breakdown Mechanisms and Lifetime Prediction for 90-nm-Node Low-Power HfSiON/SiO2 CMOSFETs

The mechanisms of gate leakage current and that of time dependent dielectric breakdown (TDDB) failure of HfSiON/SiO2 gate dielectrics having an equivalent oxide thickness of 1.6 nm were investigated. The leakage current mechanism was found to be different for low and high electric fields, which we attribute to the difference in barrier height between interfacial SiO2 and HfSiON. The mechanism of TDDB also proved to be different for low and high electric fields. Accordingly, TDDB lifetime must be evaluated in the low-gate-bias region, where the leakage current mechanism is the same as that of the actual FET operating voltages. A system for detecting defect generation using an emission microscope was developed, enabling low-bias TDDB measurements of large-gate-area transistors. Through this investigation, it was predicted that HfSiON/SiO2 has much more than 10 years' TDDB reliability.

Dependence of Time-Dependent Dielectric Breakdown Lifetime on the Structure in Cu Metallization

Time-dependent dielectric breakdown (TDDB) in Cu metallization and its dependence on the presence of a barrier metal, the kind of barrier metal, barrier metal thickness, the low-k dielectric and the low-k barrier dielectric, is investigated. There is a distinct difference between TDDB degradation mechanisms with and without barrier metals. The degradation mechanism is drift through the bulk without the barrier, but drift along the CMP surface with the barrier. The barrier property against TDDB is better for Ta and TaN than that for TiN. The TDDB characteristic is independent of the barrier metal thickness, but depends strongly on the electric field strength in the structure. The degradations, related to Cu ion diffusion, are mainly caused by electrical stress, not thermal stress. In a low-k structure, the leakage current path is along the CMP surface due to the electric field concentration. The TDDB lifetime with a barrier metal depends on the breakdown voltage of the low-k material. The TDDB lifetime decreases as the k-value becomes lower. Although the use of low-k barrier dielectrics decreases the TDDB lifetime, a satisfactory TDDB lifetime is achievable with a low-k barrier dielectric as thin as 25 nm. All low-k structures in our study satisfy the 10-year projected TDDB reliability. However, the TDDB lifetime for technology generations beyond the 65 nm-node CMOS may have inadequate 10-year reliability.

TDDB Reliability Improvement of Cu Damascene with a Bilayer-Structured α-SiC:H Dielectric Barrier

This work investigates the thermal stability and physical and barrier characteristics of two species of amorphous silicon carbide dielectric films: the nitrogen-containing α-SiCN film with a dielectric constant of 4.9 and the nitrogen-free α-SiC film with a dielectric constant of 3.8. The time-dependent-dielectric-breakdown (TDDB) lifetime of the Cu damascene metallization structure is greatly improved by using an α-SiCN/α-SiC bilayer dielectric stack as the barrier layer. This improvement is attributed to the lower leakage current of α-SiC, absence of nitridation on the Cu surface, and better adhesion of α-SiC on Cu and organosilicate glass intermetal dielectric. Although the α-SiC film has a very low deposition rate, the α-SiCN/α-SiC bilayer dielectric is a favorable combination for the barrier layer because α-SiCN can protect α-SiC from plasma attack, such as plasma attack during photoresist stripping and organosilicate plasma attack during organosilicate glass deposition. © 2004 The Electrochemical Society. All rights reserved.

A new empirical extrapolation method for time-dependent dielectric breakdown reliability projections of thin SiO 2 and nitride–oxide dielectrics

The results of an investigation of time-dependent dielectric breakdown (TDDB) of thin gate oxide and nitride–oxide (N–O) films are presented for a wide range of fields and temperatures. It was found that TDDB of both gate oxide and N–O films followed a power-law dependence of mean value ( I avg ) of average leakage current ( I avg). An empirical extrapolation model using average leakage current as a major parameter was proposed based on experimental results. This proposed ( I avg ) lifetime model has been successful to predict dielectric reliability. It could continuously fit the entire breakdown data from both wafer level and module level stress. The extrapolation from wafer level data to module data was excellent. The power of current versus TDDB showed exponential dependence on oxide thickness. This proposed TDDB projection methodology also worked for N–O films with an abrupt current increase in the I– V curve at a certain voltage well below the breakdown voltage, while the conventional models clearly failed to fit all data from this region. The observation of TDDB dependence of the current may open a new window for oxide lifetime projections and provide some insights into the nature of oxide breakdown and its implications for reliability studies.

Scalability of Gate/N- Overlapped Lightly Doped Drain in Deep-Submicrometer Regime

In this paper an experimental study of the scalability of a gate/N- overlapped lightly doped drain (OL-LDD) structure in the deep-submicrometer regime is presented. Devices were optimized for processes with a design rule down to 0.15 µm. The allowable power supply voltage is obtained by investigating the time-dependent dielectric breakdown reliability, the minimum operating voltage, the gate-induced-drain-leakage current, the drain-induced-barrier-lowering effect and the DC hot carrier reliability. It was found that the maximum allowable supply voltage is mainly limited by the DC hot carrier reliability even in the deep-submicrometer range. A higher current-driving ability in the OL-LDD structure is achieved in comparison to that in a single drain (SD) structure when VDmax is applied as a supply voltage. The OL-LDD structure has a smaller CGD in the inversion region as well as in the accumulated region, as compared with the SD structure, especially with smaller LG. Consequently, the performance of complementary metal-oxide-semiconductor (CMOS) devices with the OL-LDD structure is superior to that with the SD structure in the deep-submicrometer regime. It is also confirmed that the OL-LDD structure has a scaling merit even for 0.15 µm CMOS devices.