Time-dependent Dielectric Breakdown Measurements Research Articles

An analog to digital converter in a SiC CMOS technology for high-temperature applications

Integrated circuits based on wide bandgap semiconductors are considered an attractive option for meeting the demand for high-temperature electronics. Here, we report an analog-to-digital converter fabricated in a silicon carbide complementary metal–oxide–semiconductor technology now available through Europractice. The MOSFET component in this technology was measured up to 500 °C, and the key parameters, such as threshold voltage, field-effect mobility, and channel-length modulation parameters, were extracted. A 4-bit flash data converter, consisting of 266 transistors, is implemented with this technology and demonstrates correct operation up to 400 °C. Finally, the gate oxide quality is investigated by time-dependent dielectric breakdown measurements at 500 °C. A field-acceleration factor of 4.4 dec/(MV/cm) is obtained by applying the E model.

Dielectric breakdown behavior of ferroelectric HfO2 capacitors by constant voltage stress studied by in situ laser-based photoemission electron microscopy

In situ laser-based photoemission electron microscopy observations with time-dependent dielectric breakdown measurements of TiN/Hf0.5Zr0.5O2(HZO)/TiN ferroelectric capacitors were performed to reveal the dielectric breakdown (DB) mechanism. We succeeded in visualizing the hard DB spots through the top electrode. We found that capacitors with short- and long-lifetime distributions were broken down near and far from the edge of the capacitors, respectively. This indicates that the DB is either topography-dependent or film-quality-dependent. This work demonstrates an effective method of detecting DB in a non-destructive manner to provide an insight for achieving higher endurance HfO2-based ferroelectric capacitors.

Graphene-All-Around Cobalt Interconnect with a Back-End-of-Line Compatible Process.

The graphene-all-around (GAA) structure has been verified to grow directly at 380 °C using hot-wire chemical vapor deposition, within the thermal budget of the back end of the line (BEOL). The cobalt (Co) interconnects with the GAA structure have demonstrated a 10.8% increase in current density, a 27% reduction in resistance, and a 36 times longer electromigration lifetime. X-ray photoelectron spectroscopy and density functional theory calculations have revealed the presence of bonding between carbon and Co, which makes the Co atom more stable to resist external forces. The ability of graphene to act as a diffusion barrier in the GAA structure was confirmed through time-dependent dielectric breakdown measurement. The Co interconnect within the GAA structure exhibits enhanced electrical properties and reliability, which indicates compatibility applications as next-generation interconnect materials in CMOS BEOL.

MoS2 as an Effective Cu Diffusion Barrier with a Back-End Compatible Process.

This study demonstrates molybdenum disulfide (MoS2) as a superior candidate as a diffusion barrier and liner. This research explores a newly developed process to show how effectively MoS2 can be applied. First, a new approach is developed to prepare molybdenum disulfide (MoS2) by microwave plasma-enhanced sulfurization (MW-PES). MW-PES can rapidly and directly grow on the target substrate at low temperatures, which is compatible with the back-end-of-line (BEOL) technology. Second, the performance of MW-PES MoS2 as a diffusion barrier and liner is reported in the subsequent section. Through time-dependent dielectric breakdown (TDDB) measurements, MoS2 is shown to have a barrier property better than that of the current material, Ta, with the same thickness. According to the model fitting, the lifetime of the device is about 45.2 times the lifetime under normal operating conditions. Furthermore, MoS2 shows its superior thermal stability in maintaining the barrier properties. MoS2 is proven to be an excellent interface as a liner as it can provide sufficient adhesion and wettability to further effectively reduce the surface scattering of copper (Cu) and significantly lower the circuit resistance.

1/f noise of short-channel indium tin oxide transistors under stress

In this work, we investigate the reliability and stability of short-channel indium tin oxide (ITO) field-effect transistors through 1/f noise characterization at elevated temperature with positive bias temperature instability (PBTI). The 1/f noise behavior of a short-channel 60-nm-long channel ITO transistor can be described by the carrier number fluctuation model, suggesting that carrier trapping and de-trapping by trap states within the 5 nm thin high-κ HfLaO dielectric are the dominant mechanisms affecting 1/f noise. Small positive threshold voltage shifts of 0.042 and 0.057 V after PBTI measurements of 3000 s at 25 and 85 °C have been obtained, respectively. The higher gate leakage current at elevated temperature leads to an earlier breakdown in the time-dependent dielectric breakdown measurement. Furthermore, 1/f noise after PBTI has also been carried out at elevated temperature, and the degradations after stress can also be attributed to the stress induced traps inside the gate dielectric.

The Influence of Extended Defects in 4H-SiC Epitaxial Layers on Gate Oxide Performance and Reliability

For the ongoing commercialization of power devices based on 4H-SiC, increasing the yield and improving the reliability of these devices is becoming more and more important. In this investigation, gate oxide on 4H-SiC was examined by time-zero dielectric breakdown (TZDB) and constant current stress (CCS) time-dependent dielectric breakdown (TDDB) method in order to get insights into the influence of the epitaxial defects on the gate oxide performance and reliability. For that purpose, MOS capacitors with different gate oxides have been fabricated. Crystal defects in the epitaxial layers have been detected and mapped by ultraviolet photoluminescence (UVPL) and interference contrast (DIC) imaging. The results of the comparison of electrical data and surface mapping data indicate a negative influence on the leakage current behavior for some extended epitaxial defects. Results from TDDB measurement indicated numerous extrinsic defects, which can be traced back to gate oxide processing conditions and defect densities.

Molecular Bridges Link Monolayers of Hexagonal Boron Nitride during Dielectric Breakdown

We use conduction atomic force microscopy (CAFM) to examine the soft breakdown of monocrystalline hexagonal boron nitride (h-BN) and relate the observations to the defect generation and dielectric degradation in the h-BN by charge transport simulations and density functional theory (DFT) calculations. A modified CAFM approach is adopted, whereby 500 × 500 nm2 to 3 × 3 μm2 sized metal/h-BN/metal capacitors are fabricated on 7 to 19 nm-thick h-BN crystal flakes and the CAFM tip is placed on top of the capacitor as an electrical probe. Current–voltage (I-V) sweeps and time-dependent dielectric breakdown measurements indicate that defects are generated gradually over time, leading to a progressive increase in current prior to dielectric breakdown. Typical leakage currents are around 0.3 A/cm2 at a 10 MV/cm applied field. DFT calculations indicate that many types of defects could be generated and contribute to the leakage current. However, three defects created from adjacent boron and nitrogen monovacancies exhibit the lowest formation energy. These three defects form molecular bridges between two adjacent h-BN layers, which in turn “electrically shorts” the two layers at the defect location. Electrical shorting between layers is manifested in charge transport simulations, which show that the I-V data can only be correctly modeled by incorporating a decrease in effective electrical thickness of the h-BN as well as the usual increase in trap density, which, alone, cannot explain the experimental data. An alternative breakdown mechanism, namely, the physical removal of h-BN layers under soft breakdown, appears unlikely given the h-BN is mechanically confined by the electrodes and no change in AFM topography is observed after breakdown. High-resolution transmission electron microscope micrographs of the breakdown location show a highly localized (<1 nm) breakdown path extending between the two electrodes, with the h-BN layers fractured and disrupted, but not removed.

Doped Ru to enable next generation barrier-less interconnect

An effective method for the formation of a Zn-doped Ru liner is demonstrated that realizes a self-forming barrier to achieve low resistivity interconnects for future back-end of line interconnect nodes. The “Ru–Zn” exhibits significantly improved adhesion to the dielectric and better electrochemical nucleation as compared to those of pristine Ru. In addition, time-dependent dielectric breakdown (TDDB) measurements indicate the inhibition of Cu ions drifting into the dielectric that precedes the TDDB failure. Complementary analysis using x-ray absorption spectroscopy, transmission electron microscope, and energy dispersive spectroscope suggests that the “Ru–Zn” forms an interfacial Zn–Si–O compound, and Zn, being more electronegative than Cu, protects the latter from oxidation. Calculation using density function theory also indicates that the Zn–Si–O compound adopts an intercalated structure at the interface of Ru/dielectric in which Zn occupies the interstitial sites within the Si–O lattice. We propose a twofold mechanism for improved TDDB performance: (1) the intercalated Zn atoms effectively block the diffusion of Cu ions through the dielectric and (2) Zn provides the cathodic protection of Cu that prevents the generation of mobile Cu ions that accelerate the TDDB.

Bias-Dependent Conduction-Induced Bimodal Weibull Distribution of the Time-Dependent Dielectric Breakdown in GaN MIS-HEMTs

In this article, we investigated the bimodal behavior in the Weibull distribution of time to breakdown during time-dependent dielectric breakdown (TDDB) measurement in GaN metal–insulator–semiconductor high electron mobility transistors (MIS-HEMTs) with Si3N4 gate insulator. We propose that the gate leakage current is a mixture mechanism of Poole–Frenkel (PF) emission and Fower–Nordheim (FN) tunneling current. The dominant mechanism of devices could shift from PF emission to FN tunneling when the stress bias is above a certain value, which is related to the properties of traps in the gate dielectric. The evolution of the leakage mechanism with stress bias leads to the deviation of the Weibull slope from the original one at low stress bias, where PF emission is the dominant one.

(Invited, Digital Presentation) Improved Reliability of 4H-SiC Metal-Oxide-Semiconductor Devices Utilising Atomic Layer Deposited Layers with Enhanced Interface Quality

A major component of reliability of Silicon Carbide (4H-SiC) power electronics are due to the gate dielectric. Specific aspects such as hysteresis, insulator lifetime, threshold voltage (VTH) instability and high leakage currents, remain an issue of paramount importance which hamper the uptake of 4H-SiC power MOSFETs.1 The oxide understood to have the most importance is coincidently the native oxide, SiO2, due to the suitable band offset to 4H-SiC. However, most of the SiO2/SiC interface problems, such as carbon clusters, H content and O vacancies, are directly related to the thermal oxidation process.2 Here, we show these issues can partially be avoided by using dielectric deposition instead.Atomic layer deposition (ALD) offers specific advantages such as very low deposition temperature, excellent process control and suitability for conformal deposition of gate oxides in trench structures.3 Deposited oxides still require a post-deposition anneal (PDA) in a nitrogen-containing ambient4 such as nitrous oxide (N2O) or nitric oxide (NO) [2] to passivate the defects within the stack and improve the as-deposited layer’s poor electrical quality. We present the excellent reliability performance of ALD-deposited SiO2 layers on SiC through fabrication of metal-oxide-semiconductor capacitors (MOSCAPs) and then using time-dependent dielectric breakdown (TDDB) characterisation. The distribution of interface parameters, as well as the results from TDDB, have been investigated as metrics of improvement following the N2O PDA process. For benchmarking, processes will be compared to thermally grown oxides4 and LPCVD-deposited dielectric layers to demonstrate the superior process quality.An active 10 µm thick epitaxial layer of 4 × 1015 cm-3 n-type doping is used in this study and grown on 100 mm diameter, 4° off-axis (0001) 4H-SiC wafers. Growth was performed using a 30 μm/hr growth and N2 as a dopant in an LPE ACiS M8 chemical vapour deposition (CVD) reactor. After an initial clean, a 1 µm thick field oxide was deposited and a window was opened via photolithography and reactive ion etching (RIE). Then, quarter wafers underwent one of the three oxidation routines: 1. SiO2 plasma deposition at 200 °C using bis(diethylamino)silane (BDEAS) and O2 plasma precursors in an Ultratech Fiji G2 Plasma-Enhanced ALD System. 2. SiO2 deposition at 750 °C using tetraethyl orthosilicate (TEOS) as a precursor in a Thermco LPCVD system. 3. direct thermal growth of SiO2 in a HiTech furnace at 1300 °C for 5 hrs in N2O ambient. Samples that had undergone one of the first two routines then underwent a PDA in N2O, in the HiTech furnace at 1300°C for 2 hrs. All oxidation measurements resulted in oxide thicknesses between 50 and 60 nm, which were verified using step-height AFM measurements and optical interferometry. To create the vertical MOSCAP structure samples had a 500 nm aluminium (Al) backside contact deposited, before a 1 μm Al layer was deposited on the topside of the samples by means of a liftoff process. A cross-sectional diagram of the fabricated final device structure is shown in Fig. 1 (a). Table I shows the key electrical parameters which were extracted using room temperature C-V measurements, combined with I-V and constant field TDDB measurements at 175 °C. Fig. 1 (b) shows the improvement brought about by the N2O anneal, which also results in the average flatband voltage being reduced by more than 10 V to the lowest value of the dataset (1.44 V) and frequency dispersion mostly removed, with all but the ALD as-deposited samples reaching average breakdown oxide fields of about 10 MV/cm. The most promising improvement of the ALD-deposited SiO2 can be seen observing the breakdown distribution of MOSCAPs when stressed at constant high electric field (9 MV/cm), which can be seen in Fig. 2 (a) and (b). Here, these samples reach a TDDB, 63% value of 4786 s, which represents an average increase of 28% when compared to LPCVD samples and 58% when comparing this to a purely thermal process.Further evidence will be presented that high-quality, high-reliability SiO2 layers, formed by ALD and PDA have been formed. Flatband voltage and hysteresis are reduced, compared to thermally grown oxide, and frequency dispersion in accumulation is negligible. The ALD oxide with PDA has higher reliability than LPCVD and thermal oxides in TDDB tests, offering 29% to 345% improvement. The degradation mechanisms of the ALD oxide are different to that the LPCVD and thermal oxides and will be discussed in this talk.[1] P. Moens et al, ISPSD 32, 78-71 (2020).[2] P. Fiorenza et al, Appl. Surf. Sci., 149752 (2021).[3] A. Renz et al, MSSP 122, 105527 (2021).[4] K. Tachiki et al, Appl. Phy. Expr. 13.12, 121002(2020). Figure 1

Effect of N2-Anneal Temperature on Silicon Nitride Film: (I) Time-Dependent Dielectric Breakdown and ESR Evaluations

Silicon Nitride (SiN) film has been used as insulating material in many electronic devices such as capacitors and memories . In this report, the effect of N2 anneal temperature on charge break down (Qbd) of LP-CVD SiN film was electrically evaluated using the time-dependent dielectric breakdown (TDDB) test method, and the variation and the density of defects which exist in SiN film, in the oxide layer between SiN and Si substrate, and at the surface of Si substrate, were investigated using an Electron Spin Resonance (ESR) to reveal the defect behavior related to the trigger of Qbd.SiN metal-insulator-metal (MIM) capacitors were fabricated to evaluate TDDB. A 54 nm dielectric layer of SiN film was deposited at 700 degree-C, using a mixture of dichlorosilane（SiH2Cl2）and ammonia (NH3) gasses, by a LP-CVD vertical furnace. For the lower and upper electrode, a 400 nm polycrystalline silicon films were deposited using a LP-CVD. In order to evaluate the effect of anneal temperature on SiN film breakdown frequency, these samples were annealed in nitrogen atmosphere at temperatures between 700 and 1150 degree-C for 1 hour, using a vertical furnace.Breakdown voltage was measured with a current-voltage tester (HP4071A, Hewlett Packard) for each SiN MIM capacitor. The breakdown frequency was defined as the ratio of failed capacitors to tested capacitors. For the TDDB measurements, a constant current stress of 1.33 A/cm2 was applied to the MIM capacitors with the area of 0.00375cm2, 0.0075cm2, 0.015cm2 and 0.03cm2. For each area, 100 chips were made from one wafer and measured.In Fig.1, SiN film breakdown frequency increases toward a peak at around the N2 anneal temperature of 900 degree-C, then decreases at 1000 degree-C, and at more than 1100 degree-C, the frequency increases again drastically at 1150 degree-C.SiN films for ESR study were fabricated on Si wafer in the same LP-CVD process, and annealed in nitrogen atmosphere at temperatures between 700 and 1150 degree-C for 1 hour, using a vertical furnace.The ESR measurements were performed at room temperature using an X-band spectrometer (JES-RE1X). To improve the signal-to-noise ratio of an ESR signal waveform, we set the accumulation number of magnetic-field (H) sweep about 300 times. Mn2+/ MgO hyperfine lines were used for the g marker, and spin densities were determined by using the standard of known spin content.In Fig.2, Dangling bond density at silicon interface (Pb center) has a peak at 900 degree-C, and those in SiO2 (E’ center) and SiN film (K center) increase with increasing temperature from 1000 to 1150 degree-C. The former phenomena of Pb center coincides with the peak of SiN film breakdown frequency at 900 degree-C, and the latter one of E’ center and K center coincides with the tendency of increasing Qbd frequency at more than 1000 degree-C. Figure 1

Effects of sputtering power on the formation of 5 nm thick ferroelectric nondoped HfO2 gate insulator for MFSFET application

In this research, the effects of sputtering power on the ferroelectric property of 5 nm thick ferroelectric nondoped HfO2 were investigated for metal–ferroelectric–semiconductor field-effect-transistor application. The remnant polarization (2P r) was increased to 5.9 μC cm−2, and the density of interface states (D it) at silicon interface was effectively reduced to 1.8 × 1011 cm−2 eV−1 when the sputtering power was 50 W for 5 nm thick nondoped HfO2 formation. The largest Weibull slope (β) of 1.76 was extracted in Weibull distribution plot of the time-dependent dielectric breakdown measurements, and excellent fatigue properties until 1010 cycles were realized. The memory window of 0.56 V was realized by the pulse amplitude and width of −1/6 V and 100 ms, respectively. Furthermore, the memory characteristic was expected to be maintained ever after 10 years of retention time.

Characterization and numerical analysis of breakdown in thick amorphous SiO2 capacitors

Charge transport in thick amorphous silicon dioxide capacitors for integrated galvanic insulators is experimentally investigated and analyzed through numerical simulations carried out with a commercial TCAD tool. The material intrinsic defectivity and the large biases applied to such devices give rise to a leakage current which is responsible for degradation and failure. Hence it is crucial to have a complete understanding of the charge-transport main physical mechanisms in amorphous silicon oxide. In particular, charge injection at contacts and charge build-up due to trapping/de-trapping mechanisms in the bulk of the oxide are expected to play a crucial role and their complex coupled interaction needs to be investigated via a TCAD-based approach. For this reason, time-dependent dielectric breakdown measurements at constant-current stresses and voltage-ramp stresses up to breakdown have been performed on thick metal-insulator–metal structures, and numerical simulations have been carried out so to predict the failure mechanisms. To this purpose, special attention has been devoted to the physical modeling of defects and impact-ionization generation.

Time-Dependent Dielectric Breakdown of Commercial 1.2 kV 4H-SiC Power MOSFETs

Constant-voltage time-dependent dielectric breakdown (TDDB) measurements are performed on recently manufactured commercial 1.2 kV 4H-SiC power metal-oxide-semiconductor (MOS) field-effect transistors (MOSFETs) from three vendors. Abrupt changes of the electric field acceleration parameters ( γ) are observed at oxide electric fields ( E <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ox</sub> ) around 8.5 MV/cm to 9 MV/cm for all commercial MOSFETs. Gate leakage currents and threshold voltage shifts are also monitored under different oxide fields ( E <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ox</sub> = 8 MV/cm and 10 MV/cm). The results suggest the failure mode under high oxide electric field is modified by impact ionization or Anode Hole Injection (AHI) induced hole trapping. This observation agrees with previously published oxide reliability studies on SiC MOSFETs and suggests that constant-voltage TDDB measurements need to be carefully performed under low oxide fields to avoid lifetime overestimation caused by hole trapping. The extrapolated t <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">63%</sub> lifetimes (times to 63% failures) from TDDB measurements performed at E <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ox</sub> <; 8.5 MV/cm are longer than 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">8</sup> hours at 150°C for all vendors. The predicted lifetimes at E <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ox</sub> = 4 MV/cm demonstrate more than 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">5</sup> times increases than the oxide lifetimes reported a decade ago, showing promising progress in SiC technology.

Improving the GaN-on-GaN Schottky Barrier Diode by ALD-AlN Tunneling Barrier Layer and Multi-Fins Structure

In this paper, we report a 1.84 kV GaN-on-GaN Schottky barrier diode (SBD) corresponds to a low on-resistance of 1.98 mΩ-cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The GaN epi-layer was etched to the multi-fins-structure with optimized bevel angle. The fins structure enables to improve the breakdown voltage by means of the uniforme electric field distribution. Afterwards, the GaN fins were capped by atomic layer deposition (ALD)-grown AlN film. The AlN served as a tunneling-barrier layer, which not only passivated the GaN surface but also decreased the turn-on voltage. The AlN-capped SBD shows a turn-on voltage at 0.18 V. Furthermore, the temperature-dependent transfer characteristics suggest the different current tunneling mechanisms at low and high electric field conditions, respectively. The time-dependent dielectric breakdown (TDDB) measurement suggests the surface traps were well passivated by ALD-AlN, which implies that the AlN cap-layer enables to improve the device reliability.

Reliability Characteristics of Diamond-Like Carbon as Gate Insulator for Metal–Insulator–Semiconductor Application

This study presents the reliability of diamond-like carbon (DLC) ultrathin films fabricated by DC magnetron sputtering as the gate dielectric layer in metal–insulator–semiconductor (MIS) devices. Stress-induced leakage current (SILC) and time-dependent dielectric breakdown (TDDB) measurements were performed to determine the reliability of the devices. The MIS device with DLC film deposited at 1100-V bias exhibited little variation of SILC under different constant voltage stress times and had a long TDDB lifetime. The results indicate excellent reliability of DLC films used as gate dielectrics. Moreover, several soft breakdown events occurred during TDDB measuring. An extended percolation model was adopted for explanation of the current versus time characteristics.

Performance and Reliability Degradation of CMOS Image Sensors in Back-Side Illuminated Configuration

We present a systematic characterization of wafer-level reliability dedicated test structures in Back-Side-Illuminated CMOS Image Sensors. Noise and electrical measurements performed at different steps of the fabrication process flow, definitely demonstrate that the wafer flipping/bonding/thinning and VIA opening proper of the Back-Side-Illuminated configuration cause the creation of oxide donor-like border traps. Respect to conventional Front-Side-Illuminated CMOS Image Sensors, the presence of these traps causes degradation of the transistors electrical performance, altering the oxide electric field and shifting the flat-band voltage, and strongly degrades also reliability. Results from Time-Dependent Dielectric Breakdown and Negative Bias Temperature Instability measurements outline the impact of those border traps on the lifetime prediction.

Electrical Characterization of BEOL Plasma-Induced Damage in Bulk FinFET Technology

Due to the small size of the transistors affected by plasma-induced damage (PID), the electrical characterization of this effect is challenging. In this paper, dc characteristics, breakdown measurements and charge pumping results are combined to extract information about the impact of PID occurring during BEOL processing in an advanced bulk FinFET technology. The effect of PID is visible on the threshold voltage and the transconductance, but not on the gate current and the subthreshold swing, suggesting that fixed charges are responsible for this degradation rather than trap creation. This is confirmed with time-dependent dielectric breakdown measurements. Nonetheless, charge pumping measurements demonstrate that PID increases the density of traps by a factor 1.78, even though the absolute density of traps remain too low to affect significantly the dc characteristics of the transistors.

Influence of GaN- and Si3N4-Passivation Layers on the Performance of AlGaN/GaN Diodes With a Gated Edge Termination

This paper analyses the influence of the GaN and Si3N4 passivation (or “cap”) layer on the top of the AlGaN barrier layer on the performance and reliability of Schottky barrier diodes with a gated edge termination (GET-SBDs). Both GaN cap and Si3N4 cap devices show similar dc characteristics but a higher density of traps at the SiO2/GaN interface or/and an increase of the total dielectric constant in the access region result in higher $R_{\mathrm{ON}}$ -dispersion in GaN cap devices. The leakage current at medium/low temperatures in both types of devices shows two low-voltage-independent activation energies, suggesting thermionic and field-emission processes to be responsible for the conduction. Furthermore, a voltage-dependent activation energy in the high-temperature range occurs from low voltages in the GaN cap devices and limits their breakdown voltage ( ${V}_{\mathsf {BD}}$ ). Time-dependent dielectric breakdown measurements show a tighter distribution in Si3N4 cap devices (Weibull slope $\beta = {3.3}$ ) compared to GaN cap devices ( $\beta = 1.8$ ). Additional measurements in plasma-enhanced atomic layer deposition (PEALD)-Si3N4 capacitors with different cap layers and TCAD simulations show an electric field distribution with a strong peak within the PEALD-Si3N4 dielectric at the GET corner, which could accelerate the formation of a percolation path and provoke the device breakdown in GaN cap SBDs even at low-stress voltages.

Dielectric breakdown of alumina thin films produced by pulsed direct current magnetron sputtering

Alumina films (~2 μm thick) were deposited with a mixed Cu/Al interlayer onto copper. Direct current (DC)/Pulsed DC (PDC) magnetron sputtering techniques were independently compared for reactive alumina sputtering. In DC sputtered films, elemental aluminium of 9.2 at.% and nano-crystallites were present within the x-ray amorphous matrix, resulting from target arcing. Defects lead to premature dielectric breakdown/increased current leakage. PDC sputtering improved film quality by removing crystallites, metallic clusters and through thickness cracking. Time dependent dielectric breakdown (TDDB) measurements were carried out using conductive atomic force microscopy identified an improvement in dielectric strength (166 to 310 V μm−1) when switching from DC to PDC deposition power. TDDB suggested that at high applied field the dominant pre-breakdown conduction mechanism was Fowler-Nordheim tunnelling in DC films. Tensile pull-off adhesion ranged from 56 to 72 MPa and was highest following incorporation of an Cu/Al blended interfacial layer. Scratch testing indicated various cracking/buckling failures.