Time-dependent Dielectric Breakdown Characteristics Research Articles

Effect of electrical stress on time dependent dielectric breakdown (TDDB) tolerate capability of HfO2–ZrO2 ferroelectric films with different thicknesses

HfO2-based ferroelectric materials as the most promising candidate for the ferroelectric memories, have been widely studied for more than a decade due to their excellent ferroelectric properties and CMOS compatibility. In order to realize its industrialization as soon as possible, researchers have been devoted to improving the reliability performance, such as wake up, imprint, limited endurance, et al. Among them, the breakdown characteristic is one of main failure mechanisms of HfO2-based ferroelectric devices, which limits the write/read reliability of the devices. Based on this, we systematically studied the effect of thickness on the time-dependent dielectric breakdown (TDDB) tolerate capability of HfO2–ZrO2 (HZO) FE films under both forward and reverse electrical stress conditions. The thickness of HZO FE film ranged from 6 to 20 nm. Our findings reveal that decreasing the thickness of the HZO FE film leads to an improvement in TDDB tolerance capability which is attributed to the fact that higher density of oxygen vacancies in thinner HZO FE films can effectively inhibit the generation of new oxygen vacancies and the growth of conductive filaments, thus effectively improving the TDDB characteristics. These results provide a potential solution for mitigating breakdown characteristics of HfO2-based ferroelectric devices in memory applications.

Formation of Remote Quantum Point Contact Inside Dielectric Medium of an AlO x /SiO x ReRAM

Remote quantum point contact (QPC) far from the metal electrodes was observed in forming free aluminum oxide (AlOx)/silicon oxide (SiOx) resistive random access memory (ReRAM) cell, which was resolved at low bias. QPC behavior of the cell was attributed to confined oxygen vacancies across uncorrelated narrow grain boundaries of intermediate O3 treated thin AlOx layer of the stack, which was designed to restrict vacancy channeling between the two immediate reservoirs; i.e., from beneath SiOx to the top as-deposited AlOx layer. From time dependent dielectric breakdown (TDDB) characteristics of the cell while assessed under low stress biases, we found one to one correspondence between TDDB and its bias dependent QPC. Furthermore, we found that, under steady state and especially at low biases progressive breakdown (PBD) of the dielectric exhibited two-level random telegraph noise (RTN) like conductance fluctuations, which occurred in the magnitude of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${G}_{{0}}$ </tex-math></inline-formula> or in its multiples depending on applied bias to the cell, that demonstrated a correlation between electron trapping and maximum QPC instability during filament growth. Low voltage QPC-based switching under dc bias sweep, its correlation with TDDB and RTN under the steady state thus provided us a framework to analyze the evolution of QPC well before reaching the SET state in an AlOx/SiOx cell, which is different from the usual QPC evolution as found near contact regions in a conventional SiOx cell without accompanying engineered AlOx barrier.

Significant Differences in BTI and TDDB Characteristics of Commercial Planar SiC-MOSFETs

Silicon carbide (SiC) metal-oxide-semiconductor field-effect transistors (MOSFETs) have been produced by several vendors for commercial applications. SiC-MOSFET reliability was assessed using bias-temperature instability (BTI) and time-dependent dielectric breakdown (TDDB) characteristics. Here, we compared two planar SiC-MOSFET samples (A and B) from different vendors. The samples exhibited significantly different positive and negative BTI, time-dependent gate-current, TDDB lifetime statistics, and temperature dependence. These differences suggest NO (nitric oxide)-annealing variations.

Effects of Annealing Temperature on TiN/Hf0.5Zr0.5O2/TiN Ferroelectric Capacitor Prepared by In-Situ Like Consecutive Atomic Layer Deposition

In this letter, the ferroelectric characteristics and reliability of TiN&#x002F;Hf_0.5Zr_0.5O₂&#x002F;TiN Metal-Ferroelectric-Metal (MFM) capacitor fabricated using the <i>&#x2018;&#x2018;in-situ&#x2019;&#x2019;</i> like consecutive atomic layer deposition (<i>C-ALD</i>) and the <i>&#x201C;ex-situ&#x201D;</i> deposition techniques are compared for different post metal annealing (PMA) temperatures. We suggested that <i>C-ALD</i> deposition improves the interface of the ferroelectric HZO film and the higher PMA temperature further improves the crystal quality. We found that <i>wake-up</i> tends to happen for both types of samples with lower PMA temperature, indicating the possible higher dependence of <i>&#x201C;wake-up&#x201D;</i> on crystallinity. Nevertheless, <i>C-ALD</i> and higher PMA temperature are both required to prevent early breakdown. <i>C-ALD</i> samples combined with 600 &#x00B0;C PMA showed the excellent remanent polarization (2P_r) of 53 &#x03BC;C&#x002F;cm², endurance properties of 10¹¹ cycles, and outstanding time-dependent dielectric breakdown (TDDB) characteristics.

Reliability Analysis on TiN Gated NMOS Transistors

Compared to poly Si gate, metal gate has no gate depletions and experiences inversion capacitance gain, which makes an advantage for devices scaling. In this paper, we investigated the gate oxide leakage current and Time Dependent Dielectric Breakdown (TDDB) characteristics of TiN and poly Si electrodes with a 3.5 to 5 nm SiO2 dielectric thickness range. According to the Transmission Electron Microscope (TEM) analysis there is difference in oxide thickness. The SiO2 thickness of TiN gate electrode has been reduced by ~0.25 nm, considerably because of a scavenging effect. We normalized the reduced SiO2 thickness with an electrical oxide field, and there were no differences between the two electrodes in gate leakage current, accumulation breakdown voltage (BV), and accumulation TDDB lifetime. Therefore, we found the scavenging effect of TiN electrodes seems to affect little the leakage current and TDDB reliability of SiO2 dielectric. On the other hand, the BV and TDDB lifetime of TiN electrode in the inversion region are little bit better than that of the poly electrode. We think this differences are originated from the difference between TiN/SiO2 and poly Si/SiO2 interfaces.

Impact of O2 post oxidation annealing on the reliability of SiC/SiO2 MOS capacitors* *Project supported by the General Program of the National Natural Science Foundation of China (Grant No. 61974159) and the Youth Innovation Promotion Association of the Chinese Academy of Sciences and Scientific Instrument Developing Project of the Chinese Academy of Sciences (Grant No. YJKYYQ20200039).

The effects of dry O2 post oxidation annealing (POA) at different temperatures on SiC/SiO2 stacks are comparatively studied in this paper. The results show interface trap density (D it) of SiC/SiO2 stacks, leakage current density (J g), and time-dependent dielectric breakdown (TDDB) characteristics of the oxide, are affected by POA temperature and are closely correlated. Specifically, D it, J g, and inverse median lifetime of TDDB have the same trend against POA temperature, which is instructive for SiC/SiO2 interface quality improvement. Moreover, area dependence of TDDB characteristics for gate oxide on SiC shows different electrode areas lead to same slope of TDDB Weibull curves.

Gate leakage current reduction and improved reliability with an ultra-thin Ti layer for low-power applications

This study analyzed the physical and electrical characteristics of the interface reactions between hafnium-based high-k gate dielectrics and a TiN-based metal gate. Decreasing the N2 gas flow ratio (RN2 = N2/Ar+N2) from the physical-vapor-deposited TiN decreased the gate leakage current (JG) and the effective work function (EWF) of the metal gate. X-ray photoelectron spectroscopy analysis confirmed that TiN deposited with a lower RN2 condition can be easily oxidized to form TiOx at the gate oxide and metal gate interface after annealing at 1050 °C. This newly created oxide layer can prevent oxygen diffusion from the gate oxide through TiN to the TiN/poly-silicon interface, resulting in improved gate oxide quality. Inserting a thin Ti layer (< 1 nm) on the gate oxide formed a TiOx layer without a change in EWF, indicating that TiN composition variation followed the same trend as capacitance equivalent thickness (CET) versus JG. Therefore, an oxygen-blocking layer can have the same effect as gate oxide quality improvement for both scenarios—low RN2 of TiN and the thin Ti insertion—due to decreased oxide charge density. The Ti insertion process was associated with improved gate oxide leakage, negligible CET increase (0.2 Å), and gate oxide reliability, including time-dependent dielectric breakdown characteristics due to the blockage of oxygen up-diffusion.

Insight into gate dielectric reliability and stability of SiO2/GaN MOS devices

Gate dielectric reliability and stability of SiO2/GaN metal–oxide–semiconductor (MOS) capacitors were systematically investigated by means of area-dependent and time-dependent dielectric breakdown (TDDB) characteristics. It was found that, although high-temperature post-deposition annealing (PDA) that causes Ga diffusion in SiO2 gate dielectrics has only a minor impact on electrical properties of the SiO2/GaN interfaces, PDA at temperatures above 800 °C severely degrades dielectric reliability and stability of GaN MOS devices. Area dependences of time-zero and TDDB characteristics revealed the formation of local weak spots and generation of uniform charge trapping sites throughout the gate oxides depending on the PDA temperatures. Determinant factors for dielectric reliability of SiO2/GaN gate stacks and reasonable measures for improving their reliability and stability are discussed on the basis of the experimental findings.

High reliability CoFeB/MgO/CoFeB magnetic tunnel junction fabrication using low-damage ion beam etching

In this work, the impact of pattern edge of MgO films due to electrode separation process on its electrical reliability was investigated by measuring and analyzing I–V and time-dependent dielectric breakdown (TDDB) characteristics of MgO films with different pattern edge length. The measured TDDB lifetime at 63% drastically decreased from 1440 to 2 s when the pattern edge length increased from 32 to 320 μm, thus the electric reliability of MgO films can be significantly degraded due to the pattern edge. It was found that this issue can be solved by improving the process condition of ion bean etching (IBE), by turning the IBE angle and the IBE angle divergence. These findings can lead to high reliability magnetic tunnel junction fabrication in spin-transfer torque magnetic random access memory.

Study of the influence of gamma irradiation on long-term reliability of SiC MOSFET

ABSTRACTA study on the long-term reliability of SiC MOSFET in different operating biases under total ionizing dose radiation environment was carried out. The relationship between radiation-induced degradation of electrical parameters and time-dependent dielectric breakdown characteristics was analyzed through the energy band theory and feedback runaway model.

Proton Irradiation Effects on the Time-Dependent Dielectric Breakdown Characteristics of Normally-Off AlGaN/GaN Gate-Recessed Metal-Insulator-Semiconductor Heterostructure Field Effect Transistors.

In this work, we investigated the time-dependent dielectric breakdown (TDDB) characteristics of normally-off AlGaN/GaN gate-recessed metal–insulator–semiconductor (MIS) heterostructure field effect transistors (HFETs) submitted to proton irradiation. TDDB characteristics of normally-off AlGaN/GaN gate-recessed MISHFETs exhibited a gate voltage (VGS) dependence as expected and showed negligible degradation even after proton irradiation. However, a capture emission time (CET) map and cathodoluminescence (CL) measurements revealed that the MIS structure was degraded with increasing trap states. A technology computer aided design (TCAD) simulation indicated the decrease of the vertical field beneath the gate due to the increase of the trap concentration. Negligible degradation of TDDB can be attributed to this mitigation of the vertical field by proton irradiation.

Time-dependent dielectric breakdown of recessed AlGaN/GaN-on-Si MOS-HFETs with PECVD SiO2 gate oxide

This paper reports the first-time evaluation of the time-dependent dielectric breakdown of recessed AlGaN/GaN-on-Si metal-oxide-semiconductor heterostructure field-effect transistors (MOS-HFETs) with plasma enhanced chemical vapor deposition (PECVD) SiO2 gate oxide. The interface fixed charge density and oxide bulk charge density extracted from the flat-band voltage characteristics were 2.7 × 1011 ± 6.54 × 1010 cm−2 and -9.71 × 1017 ± 5.18 × 1016 cm−3, respectively. The time dependent dielectric breakdown (TDDB) characteristics exhibited longer lifetime estimation as the SiO2 thickness increased. The excellent reliability of the PECVD SiO2 film was validated for use as the gate oxide of recessed AlGaN/GaN MOS-HFET.

The TDDB Characteristics of Ultra-Thin Gate Oxide MOS Capacitors under Constant Voltage Stress and Substrate Hot-Carrier Injection

The breakdown characteristics of ultra-thin gate oxide MOS capacitors fabricated in 65 nm CMOS technology under constant voltage stress and substrate hot-carrier injection are investigated. Compared to normal thick gate oxide, the degradation mechanism of time-dependent dielectric breakdown (TDDB) of ultra-thin gate oxide is found to be different. It is found that the gate current (Ig) of ultra-thin gate oxide MOS capacitor is more likely to be induced not only by Fowler-Nordheim (F-N) tunneling electrons, but also by electrons surmounting barrier and penetrating electrons in the condition of constant voltage stress. Moreover it is shown that the time to breakdown (tbd) under substrate hot-carrier injection is far less than that under constant voltage stress when the failure criterion is defined as a hard breakdown according to the experimental results. The TDDB mechanism of ultra-thin gate oxide will be detailed. The differences in TDDB characteristics of MOS capacitors induced by constant voltage stress and substrate hot-carrier injection will be also discussed.

Evaluation of LPCVD SiN&lt;italic&gt;x&lt;/italic&gt; Gate Dielectric Reliability by TDDB Measurement in Si-Substrate-Based AlGaN/GaN MIS-HEMT

Si-substrate-based AlGaN/GaN high-electron mobility power transistors with low pressure chemical vapor deposition (LPCVD) SiN x as gate isolation material are fabricated on a 6-in wafer by CMOS compatible process. The dielectric failure by forward-biased constant-voltage stress time-dependent dielectric breakdown (TDDB) measurements at various temperatures (from room temperature to 250 °C) and their statistical Weibull analysis are compared. Impact of gate dielectric area and multifinger on the SiN x TDDB characteristics is also discussed. Using thermal microscope imager, the leakage current spots have been identified. The mean time to failure decreases with the increasing finger numbers in exponential form. We also predict the device ( ${W}_{G}= {0.25}$ mm) with 35-nm-thick LPCVD SiN x gate dielectric can survive at a positive gate voltage of ${V}_{\text {GS}}= {15}$ V for a 10-year time-to-breakdown lifetime (100 ppm and ${T}= {25}$ °C) and ${V}_{\text {GS}}= {7.5}$ V for a 10-year time-to-breakdown lifetime (100 ppm and ${T}= {250}$ °C).

Time-dependent dielectric breakdown of atomic-layer-deposited Al2O3 films on GaN

Atomic-layer-deposited (ALD) Al2O3 films are the most promising surface passivation and gate insulation layers in non-Si semiconductor devices. Here, we carried out an extensive study on the time-dependent dielectric breakdown characteristics of ALD-Al2O3 films formed on homo-epitaxial GaN substrates using two different oxidants at two different ALD temperatures. The breakdown times were approximated by Weibull distributions with average shape parameters of 8 or larger. These values are reasonably consistent with percolation theory predictions and are sufficiently large to neglect the wear-out lifetime distribution in assessing the long-term reliability of the Al2O3 films. The 63% lifetime of the Al2O3 films increases exponentially with a decreasing field, as observed in thermally grown SiO2 films at low fields. This exponential relationship disproves the correlation between the lifetime and the leakage current. Additionally, the lifetime decreases with measurement temperature with the most remarkable reduction observed in high-temperature (450 °C) O3-grown films. This result agrees with that from a previous study, thereby ruling out high-temperature O3 ALD as a gate insulation process. When compared at 200 °C under an equivalent SiO2 field of 4 MV/cm, which is a design guideline for thermal SiO2 on Si, high-temperature H2O-grown Al2O3 films have the longest lifetimes, uniquely achieving the reliability target of 20 years. However, this target is accomplished by a relatively narrow margin and, therefore, improvements in the lifetime are expected to be made, along with efforts to decrease the density of extrinsic Al2O3 defects, if any, to promote the practical use of ALD Al2O3 films.

First Demonstration of AlSiO as Gate Dielectric in GaN FETs; Applied to a High Performance OG-FET

Gate dielectric plays an integral role in advancing the performance and reliability of GaN-based transistors. Si-alloying of aluminum oxide (Al2O3) dielectrics have been shown to provide a promising route to improve gate dielectric properties in GaN. In this letter, we report on the first demonstration of a GaN FET with aluminum silicon oxide (AlSiO) as the gate dielectric. Vertical normally-off GaN MOSFETs were fabricated on bulk GaN substrate. Excellent dc performance was achieved with a breakdown voltage of 1.2 kV, an ON-resistance of 2 $\text{m}\Omega $ .cm2, and a threshold voltage of 1.5 V (defined at $I_{\textsf {DS}} =1\,\,\mu \text{A}$ /mm). A high breakdown electric-field of 2.3 MV/cm was calculated in these devices. In addition to vertical GaN MOSFET results, a comparative study of Al2O3 and AlSiO-based in situ GaN MOS capacitors, including time-dependent dielectric breakdown characteristics is also presented.

Breakdown Characteristics of TiN/HfxZr1-xO2/Al2O3/Ge Gate Stacks

Ge has been considered as an alternative channel material in place of Si because of its higher electron and hole mobility. Since direct deposition of high-k material on Ge leads to degradation of interface quality ultrathin Al2O3 is used as a passivation layer prior to high-k layer deposition. In addition, ZrO2/Al2O3 bilayer as gate dielectric on Ge is becoming popular since ZrO2 showed lower leakage current than HfO2 (1, 2). To further scale the effective oxide thickness (EOT) on Ge higher-k dielectric materials like Hf1-xZrxO2, with different Hf to Zr compositions has been explored. Furthermore, the recent introduction of post-deposition slot plane antenna plasma oxidation (SPAO) of the dielectric seems to enhance the interface as well as gate stack quality (3). In this work, we investigate the Time Dependent Dielectric Breakdown (TDDB) characteristics of the impact of TiN/HfxZr1-xO2/Al2O3/Ge gate stacks by changing the Zr content. Slot-plane antenna plasma oxidation (SPAO) was performed on these devices after the ALD deposition of the high-k layers. It was observed that the equivalent oxide thickness (EOT) decreases with Zr addition in HfO2 with up to 75% of Zr incorporation. With 100% Zr incorporation EOT increased significantly. This is possibly due to the formation of low-k interfacial GeO2 at the interface for 100% Zr whereas for other samples have comparatively thinner GeOx interfacial layers (3). Weibull plots shows that charge to breakdown (Q BD) increased with increase the Zr percentage. However, the breakdown acceleration factor decreased with Zr percentage up to 75% and increased rapidly for 100% Zr content. It is reported earlier (3) that GeO2 has the worst resistance to stress in terms of device stability compared to GeOx. Therefore, formation of thick GeO2 degrades the device with 100% Zr rapidly as compared to lower percentage of Zr. The authors would like to acknowledge K. Tapily, R. D. Clark, S. Consiglio, C. S. Wajda, and G. J. Leusink of TEL Technology Center, Albany, NY for their help in device preparation.

Breakdown Characteristics of TiN/HfxZr1-xO2/Al2O3/Ge Gate Stacks

This work evaluates the time dependent dielectric breakdown (TDDB) characteristics of TiN/ HfxZr1-xO2/Al2O3/Ge gate stacks by changing the Zr content and with slot-plane antenna plasma oxidation (SPAO), performed immediately after the ALD deposition of the high-k layers. It was observed that the equivalent oxide thickness (EOT) decreases with Zr addition in HfO2 with up to 75% of Zr incorporation. With 100% Zr incorporation EOT increased significantly. This is possibly due to the formation of low-k interfacial GeO2 at the interface for 100% Zr whereas for other samples have comparatively thinner GeOx interfacial layers. Weibull plots shows that charge to breakdown (Q BD) increased with increase the Zr percentage. However, the breakdown acceleration factor decreased with Zr percentage up to 75% and increased rapidly for 100% Zr content. It is, therefore, believed that GeO2 leads the TDDB degradation.

The Effect of Defects on Time Dependent Dielectric Breakdown Acceleration in TiN/ZrO2/Al2O3/p-Ge Gate Stacks

Introduction of a thin GeO2 as the interfacial layer (IL) seems to be beneficial for formation of high-k gate stacks on germanium substrate. The thickness of GeO2/GeOx impacts the overall equivalent oxide thickness (EOT) because of its low dielectric constant compared to high-k layer. Current trends indicate that the formation of appropriate thickness of GeOx or GeO2 between high-k and Ge substrate seems to have low interface state density (D it). Since ZrO2 showed lower leakage current than HfO2 with similar dielectric high-k stack, ZrO2/Al2O3 bilayer as gate dielectric is becoming popular. Even though excellent gate stacks on germanium substrate has been demonstrated the reliability and the impact of interfacial layer is still unknown. This work investigates the p-Ge/Al2O3/ZrO2/TiN gate stacks with thin GeO2 or GeOx layer, formed when the gate stack was exposed to pre- or post-deposition slot plane antenna plasma oxidation (SPAO). The post Al2O3/ZrO2 deposition SPAO forms relatively thicker GeO2 and post Al2O3 deposition SPAO forms thinner GeO2 whereas pre-deposition SPAO forms thin fragmented GeOx layer at the interface. We have observed that the relatively thicker GeO2 interfacial layer formed after the post Al2O3/ZrO2 deposition SPAO degraded faster during time dependent dielectric breakdown (TDDB) measurements on substrate injection mode compared to the thin GeO2 or GeOx interfacial layers (Fig. 1). The improvement in TDDB degradation for thinner interfacial layer thickness suggests that electrons tunnel through the thinner GeOx IL, and TDDB measured the quality of Al2O3 rather than IL. The TDDB characteristics in gate injection mode suggests that the SPAO can significantly affect the TDDB characteristics GEI mode (Fig. 1). The SPAO treatment effectively removes the trap centers in ZrO2 and Al2O3 layers when SPAO was performed after the gate stack deposition. By employing carrier transport mechanisms as a function of temperature in both gate and substrate injection mode we were able to identify the traps that contributes to the TDDB degradation. The trap center (f t1 = 0.13 eV) observed in the ZrO2 when ZrO2 is not subjected to the SPAO, i.e. pre-deposition SPAO. This trap f t1 (0.13 eV) was eliminated for post Al2O3/ZrO2 deposition SPAO. While defects in the ZrO2 layer determines the TDDB characteristics in gate injection mode the GeO2 or GeOx interfacial layer thickness determines the TDDB degradation in substrate injection mode. Figure 1

Reliability study of high-κ La2O3/HfO2 and HfO2/La2O3 stacking layers on n-In0.53Ga0.47As metal–oxide–semiconductor capacitor

This study investigates the time-dependent dielectric breakdown (TDDB) characteristics of La2O3/HfO2 and HfO2/La2O3 stacking layers on an n-In0.53Ga0.47As metal–oxide–semiconductor capacitor. Both designs improved the reliability compared with a single layer of HfO2. The TDDB followed the thermochemical E model. The current transportation mechanism changed from thermionic emission to Frenkel–Poole emission because of the traps creation under voltage stress. Both designs resulted in similar lifespans and voltage accelerating factors. However, the La2O3/HfO2 design had a longer lifespan because of the lower interface trap density and insertion of the HfO2 diffusion barrier layer between La2O3 and n-In0.53Ga0.47As. The oxide stacks exhibited excellent reliability and achieved a lifespan of 28.4 years.