Propagation Delay Time Research Articles

Optimally filtering and matching processing for regional upstrokes to improve ultrasound transit time-based local PWV estimation

Background and objectivePulse wave velocity (PWV) is an important index for quantifying the elasticity of artery. Local PWV estimates based on ultrasonic transit time (TT) methods, however, are affected by the reflected waves and ultrasonic noise, biasing the spatiotemporal propagation of the time fiduciary point (TFP) positioning in the distension waveforms. In this study, an optimally filtering and matching processing for regional upstrokes is proposed to improve the ultrasound TT-based local PWV estimation. Method(i) Smooth the pulse waves (PWs) using the Savitzky–Golay filter with one set of randomly combined parameters. (ii) An arbitrary region at the first beam upstroke of the smoothed PWs is selected as the curve template, and then matched with the upstrokes of other PWs by calculating the sum of square differences (SSD) between the template and matching regions to find its similar regions. (iii) Update the filter parameters and the template using the moth-flame optimization (MFO) feedback for computing the new SSD value. When the new SSD value is smaller than the historical one, the later will be replaced. (iv) Repeat the above steps until the MFO algorithm converges to the minimum SSD value. (v) Output the optimal filter parameters and the locations of regional curves corresponding to the minimum SSD value. Then the time delay of the PWs propagation can be detected by using the starting points of the regional curves as the TFPs. ResultsWe conducted performance comparison with the advanced TT method through both simulation and clinical experiments. The results demonstrate that the proposed work observes considerable reductions on both the normalized root mean square error ± the standard deviation (from 6.73 ± 2.27% to 1.57 ± 0.72%) and the coefficient of variation (from 13.39% to 8.87%). ConclusionsThe results of this study support that the proposed method may facilitate the early diagnosis and prevention of local arterial stiffness .

Real-time measurement system for overlapping reflection signals of fiber Bragg gratings using high-speed wavelength-swept laser

We propose a real-time measurement system that prevents overlapping reflection signals in fiber Bragg gratings (FBGs). The system combines a wavelength-swept laser using Fourier domain mode-locking (FDML) and a buffer stage with three optical paths to obtain a high-speed measurement rate of 304.2 kHz. Systems using high-speed wavelength-swept lasers are affected by the propagation time (delay) of the optical fiber. The delay causes problems such as inaccurate measurements, difficulty in distinguishing FBG reflection signals, and overlapping FBG reflection signals. To prevent these problems, we introduce a method for pulse modulation of a wavelength-swept laser by a fiber switch. This method allows for correction of delays by extracting and identifying only the reflection signal of the FBG at a specific wavelength. By identifying the reflection signals of all FBGs, the overlapping signals can be determined. Accordingly, we devise a measurement method that uses a fiber switch to shade light in the wavelength region of one FBG with overlapping signals from the wavelength-swept light of the laser. This method suppresses overlapping and allows only the reflection signal of the other FBGs to be extracted and demodulated. The proposed system uses bidirectional forward and backward scans with the wavelength-swept laser, such that the shaded FBG signals can be demodulated with either scanning direction. We demonstrate that the system using a three-buffered FDML laser can simultaneously measure the strain or vibration of FBGs installed at arbitrary distances.

The Performance Enhancement of PMOSFETs and Inverter Chains at Low Temperature and Low Voltage by Removing Plasma-Damaged Layers

In this work we report on the improvement in cold temperature characteristics of PMOSFETs and inverter circuits by removing the plasma-damaged layer of the source/drain contacts. We removed the plasma-induced damage on the Si using a simple in situ Si soft treatment technique. We found by transmission electron microscope (TEM) analysis that the damaged amorphous layer reduced from 52 Å to 42 Å and 35 Å with a treatment time of 10 and 20 s, respectively. As a result, the resistances of both the n+ and p+ contacts decreased for all contact sizes and the standard deviations at the cold temperature were suppressed by 45%. At −25 °C, the saturation current of the PMOSFET increased by 3% and the propagation delay time (tPD) decreased by 2%. The tPD increases by 19.3% when the temperature decreases from 85 °C to −25 °C, and the operating voltage decreases from 1.2 V to 0.95 V at the same time. However, this increase can be reduced to 17% by applying the soft treatment for 10 s. This simple and short time process will be considered essential for both mobile applications and automotive applications of dynamic random access memory (DRAM) devices requiring a low-voltage and low-temperature operation.

High Performance Organic Electrochemical Transistors and Logic Circuits Manufactured via a Combination of Screen and Aerosol Jet Printing Techniques

AbstractThis work demonstrates a novel fabrication approach based on the combination of screen and aerosol jet printing to manufacture fully printed organic electrochemical transistors (OECTs) and OECT‐based logic circuits on PET substrates with superior performances. The use of aerosol jet printing allows for a reduction of the channel width to ≈15 µm and the estimated volume by a factor of ≈40, compared to the fully screen printed OECTs. Hence, the OECT devices and OECT‐based logic circuits fabricated with the proposed approach emerge with a high ON/OFF ratio (103–104) and remarkably fast switching response, reaching an ON/OFF ratio of >103 in 4–8 ms, which is further demonstrated by a propagation delay time of just above 1 ms in OECT‐based logic inverter circuits operated at a frequency of 100 Hz. All‐printed monolithically integrated OECT‐based five‐stage ring oscillator circuits further validated the concept with a resulting self‐oscillation frequency of 60 Hz.

HIGH PERFORMANCE D FLIP FLOP BASED ON GNRFET

In Digital Electronic, As we know the most widely used flip flop is D flip flop which is an edgetriggered device that allows the transfers input data from Q on clock rising or falling edge. Its widely used for storage and circuits registers. For making it effectively use we always make some improvements in a better performance like Power characteristics and energy dissipation, gate leakage. Researchers have developed various types of models of static and dynamic D flip flops with various changes in their efficiency and powersaving but still, we have various ways to implement it and making it effectively useful. So I try to implement it by using Graphene Nano Ribbon Field Effect Transistor (GNRFET) in 22nm technology length of the channel with a concept of power getting for saving energy from being dissipated unnecessarily. The proposed circuit according to the simulation results in HPSICE software is proved to be better in terms of Average power, propagation time delay, Energy Dissipation. Also, voltage source power dissipation is nearly the same in GNRFETs configuration and much better in case of comparison with the bulk CMOS MOSFET counterpart. That is shown by Graphical representation in this paper. GNRFET with power gating proved as the promising substitute under the 22nm category of channel length technology.

RSS/TDoA-Based Source Localization in Microwave UWB Sensors Networks Using Two Anchor Nodes.

The manuscript presents an algorithm for the optimal estimation of the amplitude and propagation delay time of an ultra-wideband radio signal, in systems for the passive location of fixed targets based on the hybrid RSS/TDoA method in two-dimensional space with two base stations. The optimal estimate is based on the Bayesian strategy of maximum a posteriori probability density, taking into account a priori data on the statistical properties of the Line of Sight radio channel during Gaussian monocycle propagation. The Bayesian Cramer–Rao lower bound (BCRLB) of the delay time and the amplitude estimates for a time-discrete signal are calculated, and the resulting parameter estimate is compared with BCRLB. An algorithm has been developed for optimal estimation of distances from the radiation source to base stations, based on the results of the measurements of the amplitude and the propagation delay time of the UWB radio signal. The calculation of the statistical characteristics of the obtained estimate is carried out, and the functional dependence of the characteristics on various parameters is analyzed.

Attenuation Characteristics and Time Delay of PD Electromagnetic Wave Propagation in GIS Systems

Modeling of electromagnetic wave propagation inside a gas-insulated switchgear structure can be helpful for understanding and improving the utilization of partial discharge detection by providing information to help determine more optimal positioning of ultra-high frequency sensors. This paper studies the effect of insulating spacers, L- and T-type structures on electromagnetic wave propagation by simulating the time dependent wave propagation behavior for these arrangements within a gas-insulated switchgear busbar geometry. The attenuation characteristics and time delays produced by spacers, L- and T-type structures for partial discharge electromagnetic wave propagation behavior are presented. Emphasis is placed on comparison of attenuation characteristics and time delay between different observation points along the busbar both before and after the 90° bends formed by L- and T-type structures. Moreover, a comparative analysis of the radial electric field at the gas-insulated switchgear tank and its rate of change with time is also conducted. The paper demonstrates that if the location of the ultra-high frequency sensor is chosen appropriately based on knowledge of the physical structures, the attenuation effects introduced by L- and T-type structures could be reduced.

DESIGN AND SIMULATION OF LOGIC CIRCUITS AT NANO SCALE BEYOND 32 NANO METERS (FINFET)

With advancement in electronic circuitry, efforts are made to minimize chip size and to attain the desired performance so on changing one parameter the other parameters are effected like variables of field effect transistor like length and width are key variables available to the circuit designer to optimize circuit performance .When in FET’s like CMOS (complementary metal oxide semiconductor) the dimensions are decreased, the short channel effect arises and creates a problem of concern. With this effect an exponential increase in the leakage current happens. In order to reduce the SCE and hence leakage current, a new technology came into being in recent years in which a 3D multiple gate CMOS like FinFet (Fin Field Effect Transistor) has been developed which possess advantages over conventional FET’s and has attracted many engineers and designers to make it more sophisticated. This technology works in the nano meter range to minimize short channel effects. Many companies like Intel, advanced micro device, global foundries have started using FinFet technology. I have carried out my work on the basis of current researches on FinFet technology and how FinFet technology can be used in future to design new logic and memory devices like Inverter, MUX etc. Various parameters of FinFet like reduced short channel effects, less leakage current, low power consumption, less propagation delay and less time delay are discussed. Various mathematical models and software were used to simulate power, delay, power delay product, average power dissipation and energy delay products, this technology was designed to eliminate the problem of SCE by permitting transistors to be scaled down into sub 20nm range. Use of PMT model to design different logic devices at 16nm technology and analyzed output of each circuit. Parameters like Power dissipation, time delay and PDP were compared between MOSFET (CMOS) technology and FinFet technology for each circuit.

Design of JL-CFET (junctionless complementary field effect transistor)-based inverter for low power applications

Junctionless complementary field effect transistor (JL-CFET) is an emerging device that needs a small layout area and low fabrication cost. However, in order for the JL-CFET to be adopted for low power applications, two main constraints need to be overcome: (a) a high work function of metal gate and (b) a low drain current. In this work, an optimal device design is proposed to overcome those problems, by analyzing various performance metrics, such as on-state drive current, subthreshold swing, drain induced barrier lowering, propagation delay time, and ring oscillator’s oscillation frequency, which are extracted from various structures of JL-CFET. In addition, the negative capacitance effect in JL-CFET is examined to address the limit from device structures.

Striated Muscle Evaluation Based on Mechanical Impulse Propagation Speed and Delay Time During 21-Day Dry Immersion Experiment

Striated Muscle Evaluation Based on Mechanical Impulse Propagation Speed and Delay Time During 21-Day Dry Immersion Experiment

3Pa5-1 Synthetic aperture imaging with numerical simulation of propagation delay time of transmitted wave

3Pa5-1 Synthetic aperture imaging with numerical simulation of propagation delay time of transmitted wave

A new truncation algorithm of low hardware cost multiplier

Multiplier is one of the most inevitable arithmetic circuit in digital signal design. Multipliers dissipate high power and occupy significant amount of the die area. In this paper, a low-error architecture design of the pre-truncated parallel multiplier is presented. The coefficients word length has been truncated to reduce the multiplier size. This truncation scaled down the gate count and shortened the critical paths of partial product array. The statistical errors of the designed multiplier are calculated for different pre-truncate values and compared. The multiplier is implemented using Stratix III, FPGA device. The post fitting report is presented in this paper, which shows a saving of 36.9 % in resources usage, and a reduction of 17 % in propagation time delay.

Radio signal time delay estimation performance of TDOA/SSR-based source localization systems

The work is devoted to the development of an algorithm for the optimal Radio Signal Time Delay Estimation Performance in passive location systems of stationary targets based on the TDOA method in two-dimensional space. A realistic model of the radio signal at the input of sensors (base station receivers) is considered, considering the random power value as a function of the distance to the source. The optimal estimate is based on the strategy of maximum posterior probability density. The calculation of the statistical characteristics of the obtained estimate of the radio signal delay time is carried out. The Bayesian Cramér - Rao lower bound (BCRLB) of the latency estimate is calculated. It is shown that the use of a priori statistical information on the path loss of a radio signal model can improve the accuracy of estimating the propagation delay time of a radio signal in TDOA/SSR-Based Source Localization Systems.

Relay Selection for Capacity Increase in Underwater Acoustic Sensor Network.

In long distance sensor nodes, propagation delay is the most crucial factor for the successful transmission of data packets in underwater acoustic sensors networks (UWAs). Therefore, to cope with the problem of propagation delay, we propose examining and selecting the best relay node (EBRN) technique based on checking the eligibility and compatibility of RN and selecting the best RN for UWAs. In the EBRN technique, the source node (S) creates a list of the best RNs, based on the minimum propagation delay to the midpoint of a direct link between S and the destination node (D). After that, the S attaches the list of selected RNs and transmit to the D along with data packets. Finally, from the list of selected RNs, the process of retransmission is performed. To avoid collision among control packets, we use a backoff timer that is calculated from the received signal strength indicator (RSSI), propagation delay and transmission time, whereas the collision among data packets is avoided by involving single RN in a particular time. The performance of the proposed EBRN technique is analyzed and evaluated based on throughput, packet loss rate (LR), packet delivery ratio (PDR), energy efficiency, and latency. The simulation results validate the effectiveness of the proposed EBRN technique. Compared with the existing schemes such as underwater cooperative medium access control (UCMAC) and shortest path first (SPF), the proposed EBRN technique performs remarkably well by increasing the throughput, PDR, and energy efficiency while decreasing the latency and LR in UWAs.

Impact of Bias Temperature Instabilities on the Performance of Logic Inverter Circuits Using Different SiC Transistor Technologies

All electronic devices, in this case, SiC MOS transistors, are exposed to aging mechanisms and variability issues, that can affect the performance and stable operation of circuits. To describe the behavior of the devices for circuit simulations, physical models which capture the degradation of the devices are required. Typically compact models based on closed-form mathematical expressions are often used for circuit analysis, however, such models are typically not very accurate. In this work, we make use of physical reliability models and apply them for aging simulations of pseudo-CMOS logic inverter circuits. The model employed is available via our reliability simulator Comphy and is calibrated to evaluate the impact of bias temperature instability (BTI) degradation phenomena on the inverter circuit’s performance made from commercial SiC power MOSFETs. Using Spice simulations, we extract the propagation delay time of inverter circuits, taking into account the threshold voltage drift of the transistors with stress time under DC and AC operating conditions. To achieve the highest level of accuracy for our evaluation we also consider the recovery of the devices during low bias phases of AC signals, which is often neglected in existing approaches. Based on the propagation delay time distribution, the importance of a suitable physical defect model to precisely analyze the circuit operation is discussed in this work too.

Time-sensitive Positive Influence Maximization in signed social networks

Influence maximization (IM) in social networks has attracted a wide variety of studies motivated by applications like spread of ideas or innovations in a network and viral marketing of products. How to integrate the factors affecting influence diffusion into influence maximization is an key research direction. Timeliness of influence diffusion and the polarity of influence itself are two important factors, which have been used to extend IM problem by researchers. However, all existing studies only focused on one of two factors individually, this will lead time delay of influence propagation or inaccurate influence estimation. Aiming at this drawback, we propose the Time-sensitive Positive Influence Maximization (TP-IM) problem considering two factors simultaneously, to select the seed node set achieving maximum positive influence spread within the specified time limit. Furthermore, we construct the Heat Diffusion-based Polarity Influence Diffusion (HDPID) model and an improved k-Step Greedy seed node selection algorithm, to solve the TP-IM problem. Experimental results on three signed social network datasets, Epinions, Slashdot, and Wikipedia demonstrate that our method outperforms state-of-the-art methods in terms of positive influence spread with time limit.

A new method for resolving phase ambiguity in radio interferometry using Earth rotation synthesis

As a key technique in deep space navigation, radio interferometry can be used to determine the accurate location of a spacecraft in the plane-of-sky by measuring its signal propagation time delay between two remote stations. To improve the measurement accuracy, differential phase delay without phase ambiguity is usually desired. Aiming at the difficulties of resolving phase ambiguity with few stations and narrowband downlink signals, a new method is proposed in this work by taking advantage of the Earth rotation. The high accurate differential phase delay between the spacecraft and a calibrator can be achieved not only in the in-beam observation mode but also in the out-of-beam observation mode. In this paper we firstly built the model of phase ambiguity resolution. Then, main measurement errors of the model are analyzed, which is followed by tests and validations of the model and method using the tracking data of the Cassini mission and Chang’E-3 mission. The results show that the phase ambiguities can be correctly resolved to generate a 10-picosecond level accuracy differential phase delay. Angular measurement accuracy of the Cassini reaches the milli-arc-second level, and the relative position accuracy between the Chang’E-3 rover and lander reaches the meter level.

Impact of ion implantation on stacked oxide cylindrical gate junctionless accumulation mode MOSFET: An electrical and circuit level analysis

This article analyses the effect of ion implantation on electrical and circuit-level characteristics of stacked oxide cylindrical gate (CG) junctionless accumulation mode (JAM) MOSFET. Ion implantation and subsequent annealing create a Gaussian type doping profile inside the channel. A detailed study of electrical characteristics such as: drain current, threshold voltage, Ion/Ioff, transconductance (gm), output conductance (gd), capacitances (Cgs, Cgd, Cgg), unit gain frequency (fT), transit time (τ), transconductance frequency product (TFP) and gain bandwidth (GBW) product have been performed. Further, an inverter has been designed with a complimentary p-MOSFET and a lookup table-based Verilog-A model has been generated for the same. Various dc and transient parameters such as noise margin, rise time, fall time propagation delay, voltage overshoot, average current, and power dispassion have been analyzed in detail. Henceforth, a 6 T SRAM cell has been implemented with ion-implanted stacked oxide CG-JAM MOSFET and read margin, write margin, access time and N-curve analysis have been performed. Various figures of merits (FOMs) have also been studied for the device at the circuit level. All the device simulations have been performed using a 3-D TCAD tool from COGENDA. Verilog-A model-based circuit simulations have been done in the Cadence-Virtuoso platform.

High-Speed Interrogation System for Fiber Bragg Gratings With Buffered Fourier Domain Mode-Locked Laser

We develop a high-speed interrogation system with a wavelength-swept laser for sensing multiplexed fiber Bragg gratings (FBGs). High-speed and multipoint sensing is achieved by means of a buffered Fourier domain mode-locked (FDML) laser, a recently proposed high-speed wavelength-swept laser. This laser increases the measurement rate several times by tailoring the laser output with a buffer stage. The developed buffered FDML laser successfully achieves a measurement rate of 202.8 kHz using a general FDML laser driven at a sweep rate of 50.7 kHz. In order to detect reflection signals of FBGs at the high measurement rate, the measurement system introduces digital signal processing using a field programmable gate array (FPGA). However, FBG measurements with wavelength-swept lasers are affected by the propagation time (delay) in the optical fiber connecting from the laser to the FBG sensor, which reduces measurement accuracy. To overcome this limitation, the developed system uses a delay correction method with bidirectional sweep of the buffered FDML laser. The interrogation system with the buffered FDML laser achieves a time resolution of 4.9 μs without being affected by the delay.

Improved Glasius bio-inspired neural network for target search by multi-agents

This paper focuses on solving the multi-agent cooperative target search problem with the demand for obtaining the maximal cumulative detection reward, given the prior target probability map and the sensor detection ability under various constraints. First, a topologically organized model of Glasius bio-inspired neural network (GBNN) is constructed individually for each agent in order to represent the searching environment. The neural activities are determined not only by the activity propagation among neurons, but also by the external input containing the single detection reward and various constraints synthetically. Then, the agent’s searching motion can be selected greedily based on the dynamic activity landscape of GBNN. With the disadvantages of propagation time delay and activity attenuation, however, the relatively global mechanism in GBNN may lead to unsatisfactory performance or even fail to avoid the local optimal problem. Hence the Gaussian mixture model (GMM) is utilized to extract the high-value subregions and compute the future detection reward quantitatively, which can be introduced into the neuron’s external excitatory input of GBNN directly. The simulation results verify the high efficiency and strong robustness of GBNN-GMM in the searching scenarios.