HIGH PERFORMANCE D FLIP FLOP BASED ON GNRFET

Abstract

In Digital Electronic, As we know the most widely used flip flop is D flip flop which is an edgetriggered device that allows the transfers input data from Q on clock rising or falling edge. Its widely used for storage and circuits registers. For making it effectively use we always make some improvements in a better performance like Power characteristics and energy dissipation, gate leakage. Researchers have developed various types of models of static and dynamic D flip flops with various changes in their efficiency and powersaving but still, we have various ways to implement it and making it effectively useful. So I try to implement it by using Graphene Nano Ribbon Field Effect Transistor (GNRFET) in 22nm technology length of the channel with a concept of power getting for saving energy from being dissipated unnecessarily. The proposed circuit according to the simulation results in HPSICE software is proved to be better in terms of Average power, propagation time delay, Energy Dissipation. Also, voltage source power dissipation is nearly the same in GNRFETs configuration and much better in case of comparison with the bulk CMOS MOSFET counterpart. That is shown by Graphical representation in this paper. GNRFET with power gating proved as the promising substitute under the 22nm category of channel length technology.