Through-wafer Interconnects Research Articles

Fabrication of 32×32 2 D CMUT Arrays on a Borosilicate Glass Substrate With Silicon- Through-Wafer Interconnects Using Non- Aligned and Aligned Anodic Bonding

Fabrication of 32×32 2 D CMUT Arrays on a Borosilicate Glass Substrate With Silicon- Through-Wafer Interconnects Using Non- Aligned and Aligned Anodic Bonding

Two-sided through-wafer interconnect for optical spiral delay line

True-time-delay devices could significantly contribute to improving the performance of many optical systems in applications such as sensing, ranging, communication and signal processing. Delay devices based on spiral optical waveguides are of special interest due to their small size and relatively low power attenuation. In this paper, we propose to fabricate spirals on both sides of a wafer, where the coupling between them is through a vertical interconnect. The novel through-wafer interconnect has a level of attenuation that compares competitively with that obtained with a conventional s-shaped interconnect between two interleaved spirals and considerably simplifies the waveguide design and fabrication.

Fabrication of Vacuum-Sealed Capacitive Micromachined Ultrasonic Transducers With Through-Glass-Via Interconnects Using Anodic Bonding

This paper presents a novel fabrication method for vacuum-sealed capacitive micromachined ultrasonic transducer (CMUT) arrays that are amenable to 3D integration. This paper demonstrates that MEMS structures can be directly built on a glass substrate with preformed through-glass-via (TGV) interconnects. The key feature of this new approach is the combination of copper through-glass interconnects with a vibrating silicon-plate structure suspended over a vacuum-sealed cavity by using anodic bonding. This method simplifies the overall fabrication process for CMUTs with through-wafer interconnects by eliminating the need for an insulating lining for vias or isolation trenches that are often employed for implementing through-wafer interconnects in silicon. Anodic bonding is a low-temperature bonding technique that tolerates high surface roughness. Fabrication of CMUTs on a glass substrate and use of copper-filled vias as interconnects reduce the parasitic interconnect capacitance and resistance, and improve device performance and reliability. A 16×16-element 2D CMUT array has been successfully fabricated. The fabricated device performs as the finite-element and equivalent circuit models predict. A TGV interconnect shows a 2-Ω parasitic resistance and a 20-fF shunt parasitic capacitance for 250-μm via pitch. A critical achievement presented in this paper is the sealing of the CMUT cavities in vacuum using a PECVD silicon nitride layer. By mechanically isolating the via structure from the active cells, vacuum sealing can be ensured even when hermetic sealing of the via is compromised. Vacuum sealing is confirmed by measuring the deflection of the edge-clamped thin plate of a CMUT cell under atmospheric pressure. The resonance frequency of an 8-cell 2D array element with 78-μm diameter circular cells and a 1.5-μm plate thickness is measured as 3.32 MHz at 15-V dc voltage (80% V pull-in ). [2016-0200].

Glass reflow process for microsystem applications

This paper reports on a glass reflow process and its applications to microsystems. Glass compounded silicon structures are achieved using a silicon mold under a high temperature environment, a long process time and assistance of enhancement of the surface wettability. Three applications employing the glass reflow process have been proposed and investigated. Firstly, the silicon through-wafer interconnects, embedded inside the Tempax glass, have been successfully demonstrated and show a resistance of about 10 Ω per feed-through. Secondly, a thick glass layer for thermal isolations is reported. The compounded glass can thermally isolate the heated silicon with a temperature difference of more than 100 °C when the temperature of the silicon part is 140 °C at an input power of 200 mW. Additionally, the silicon micro-heater is also evaluated for its reliability. Lastly, glass capillaries and pillars with and without liquid penetration have been proposed for obtaining the high resolution light field information. The optical windows integrated with an image sensor for an optical modulator are clearly demonstrated and a light modulation effect dependent on liquid penetration is observed.

Fabrication of Vacuum-Sealed Capacitive Micromachined Ultrasonic Transducer Arrays Using Glass Reflow Process.

This paper presents a process for the fabrication of vacuum-sealed capacitive micromachined ultrasonic transducer (CMUT) arrays using glass reflow and anodic bonding techniques. Silicon through-wafer interconnects have been investigated by the glass reflow process. Then, the patterned silicon-glass reflow wafer is anodically bonded to an SOI (silicon-on-insulator) wafer for the fabrication of CMUT devices. The CMUT 5 × 5 array has been successfully fabricated. The resonant frequency of the CMUT array with a one-cell radius of 100 µm and sensing gap of 3.2 µm (distance between top and bottom electrodes) is observed at 2.84 MHz. The Q factor is approximately 1300 at pressure of 0.01 Pa.

Mapping stresses in high aspect ratio polysilicon electrical through-wafer interconnects

Electrical through-wafer interconnect technologies such as vertical through-silicon vias (TSVs) are essential in order to maximize performance, optimize usage of wafer real estate, and enable three-dimensional packaging in leading edge electronic and microelectromechanical systems (MEMS) products. Although copper TSVs have the advantage of low resistance, highly doped polysilicon TSVs offer designers a much larger range of processing options due to the compatibility of polysilicon with high temperatures and also with the full range of traditional CMOS processes. Large stresses are associated with both Cu and polysilicon TSVs, and their accu- rate measurement is critical for determining the keep-out zone (KOZ) of transistors and for optimizing down- stream processes to maintain high yield. This report presents the fabrication and stress characterization of 400-μm deep, 20-Ω resistance, high aspect ratio (25:1) polysilicon TSVs fabricated by deep reactive ion etching (DRIE) followed by low-pressure chemical vapor deposition (LPCVD) of polysilicon with in-situ boron doping. Micro-Raman imaging of the wafer surface showed a maximum stress of 1.2 GPa occurring at the TSV edge and a KOZ of ∼9 to 11 μm. For polysilicon TSVs, the stress distribution in the TSVs far from the wafer surface(s) was not previously well-understood due to measurement limitations. Raman spectroscopy was able to overcome this limitation; a TSV cross section was examined and stresses as a function of both depth and width of the TSVs were collected and are analyzed herein. An 1100°C postanneal was found to reduce average stresses by 40%. © 2015 Society of Photo-Optical Instrumentation Engineers (SPIE) (DOI: 10.1117/1.JMM.14.2.024001)

Silicon-Embedding Approaches to 3-D Toroidal Inductor Fabrication

This paper presents complementary-metal-oxide-semiconductor-compatible silicon-embedding techniques for on-chip integration of microelectromechanical-system devices with 3-D complex structures. By taking advantage of the “dead volume” within the bulk of the silicon wafer, functional devices with large profile can be embedded into the substrate without consuming valuable die area on the wafer surface or increasing the packaging complexity. Furthermore, through-wafer interconnects can be implemented to connect the device to the circuitry on the wafer surface. The key challenge of embedding structures within the wafer volume is processing inside deep trenches. To achieve this goal in an area-efficient manner, straight-sidewall trenches are desired, adding additional difficulty to the embedding process. Two approaches to achieve this goal are presented in this paper, i.e., a lithography-based process and a shadow-mask-based process. The lithography-based process utilizes a spray-coating technique and proximity lithography in combination with thick epoxy processing and laminated dry-film lithography. The shadow-mask-based process employs a specially designed 3-D silicon shadow mask to enable simultaneous metal patterning on both the vertical sidewall and the bottom surface of the trench during deposition, eliminating multiple lithography steps and reducing the process time. Both techniques have been demonstrated through the embedding of the topologically complex 3-D toroidal inductors into the silicon substrate for power supply on-chip (PwrSoC) applications. Embedded 3-D inductors that possess 25 turns and a diameter of 6 mm in a silicon trench of 300-μm depth achieve overall inductances of 45-60 nH, dc resistances of 290-400 mΩ, and quality factors of 16-17.5 at 40-70 MHz.

Development of a 3-D Process Technology for Wafer-Level Packaging of MEMS Devices

This paper presents a simple and low-cost 3-D process technology for the wafer-level packaging (WLP) of microelectromechanical system (MEMS) devices. A small-sized WLP (1.0 × 1.0 × 0.35 mm) with a hermetically sealed cavity for the moving parts of MEMS devices was fabricated by using specially designed processes. The WLP was developed using three key techniques: through-wafer interconnection, wafer bonding, and bilateral face-MEMS fabrication. The expense and complexity of processes such as silicon deep reactive ion etching and electroplating that arise from bilateral processing for through-wafer interconnection were overcome by using bulk micromachining technology. The fabricated WLP chips with a bonding area of 0.314 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> showed an average shear strength of 9.74 kg/mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and a leak rate less than 7 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-10</sup> mbar.cc/sec. In addition, the chips had less than 0.1 dB insertion loss before and after reliability testing. This newly developed 3-D process technology is a good candidate for WLP MEMS fabrication because it is simple and cost-effective.

A Wafer-Level Vacuum Package Using Glass-Reflowed Silicon Through-Wafer Interconnection for Nano/Micro Devices

We propose a vacuum wafer-level packaging (WLP) process using glass-reflowed silicon via for nano/micro devices (NMDs). A through-wafer interconnection (TWIn) substrate with silicon vias and reflowed glass is introduced to accomplish a vertical feed-through of device. NMDs are fabricated in the single crystal silicon (SCS) layer which is formed on the TWIn substrate by Au eutectic bonding including Cr adhesion layer. The WLPof the devices is achieved with the capping glass wafer anodically bonded to the SCS layer. In order to demonstrate the successful hermetic packaging, we fabricated the micro-Pirani gauge in the SCS layer, and packaged it in the wafer-level. The vacuum level inside the packaging was measured to be 3.1 Torr with +/- 0.12 Torr uncertainty, and the packaging leakage was not detected during 24 hour after the packaging.

Upside down T-shape through-wafer interconnects for fully tileable photodiode matrix for medical CT imaging

This paper presents a technology of a fully tileable two-dimensional photodiode matrix for medical imaging, specifically X-ray Computed Tomography (CT). A key trend in the CT industry is to build imaging devices with ever larger area detectors to speed up the measurements and to avoid image blurring due to patient movement. If individual slices have been taken at different points of time, the patient may have moved. The reconstruction accuracy suffers, resulting into blurred or distorted images. This can be avoided by increasing the amount of slices recorded in single rotation, up to the length of the whole object to be imaged. In most of the current CT detector constructions the characteristic pitch of the photodiodes is ∼1mm with 16×16 to 16×32 photodiodes on one chip. A major limiting factor in providing more detector coverage is the need to read out the signals from the individual photodiode elements of the photodiode matrix through metal lines between the photodiode elements along the surface facing the radiation source, and wire bonds down to a substrate or to an electronics chip. With this method, there is a physical limitation on the size of a photodiode matrix that may be manufactured. A detector with the possibility of active area expansion is known as a ‘tileable’ detector. Various technologies have been proposed to realize a tileable detector, all having their specific limitations. An improved technology of integrating T-shaped through-wafer interconnects within traditional front illuminated photodiodes is introduced, overcoming most of the limitations of the other tileable technologies. Photocurrent signal can be read out from back side of the chip through these interconnects, giving possibility of constructing arbitrarily large area of photodiode matrix. Results of an actual CT detector photodiode manufactured with this technology are presented showing that the requirements of modern CT systems can be met.

Design and Fabrication of Microelectromechanical Systems Probe Card with Vertical Trench Guide for Fine Pitch Probing

In this study, we developed a new microelectromechanical systems (MEMS) probe card with a vertically guided and electroplated cantilever in order to overcome pitch limitation, which has a compliant structure and is capable of a 35 µm pad pitch, with through-wafer interconnections for IC testing. We also investigated the reliability of the MEMS probe card using tribology and scaling of the MEMS probe card for fine pitch probing. The measured contact resistance was less than 0.5 Ω at 1.5 gf applied force and the leakage current was approximately 10 pA between one tip and an adjacent tip. In addition, the planarity of tips and the alignment of x- and y-axes were satisfied with a conventional needle probe card performance. Therefore, this probe card is suitable for wafer-level burn-in testing and function testing of memory and RF devices.

Design and Fabrication of Microelectromechanical Systems Probe Card with Vertical Trench Guide for Fine Pitch Probing

In this study, we developed a new microelectromechanical systems (MEMS) probe card with a vertically guided and electroplated cantilever in order to overcome pitch limitation, which has a compliant structure and is capable of a 35 µm pad pitch, with through-wafer interconnections for IC testing. We also investigated the reliability of the MEMS probe card using tribology and scaling of the MEMS probe card for fine pitch probing. The measured contact resistance was less than 0.5 Ω at 1.5 gf applied force and the leakage current was approximately 10 pA between one tip and an adjacent tip. In addition, the planarity of tips and the alignment of x- and y-axes were satisfied with a conventional needle probe card performance. Therefore, this probe card is suitable for wafer-level burn-in testing and function testing of memory and RF devices.

Development of Through-Wafer Interconnects for MEMS Deformable Mirrors

A MEMS deformable mirror (DM) packaging process development effort is described. This development provides a path towards direct integration of future large actuator count optical MEMS arrays (> 4000) with underlying driver electronics. Characteristic features of the packaging process include creating electrical interconnection paths through the silicon wafer for each actuator, depositing gold bump bonds on the backside of the wafer, and fusing that array of bump bonds to an interposer substrate. This process differs from existing processes for MEMS arrays, which generally employ lithographically patterned wire-routing and peripheral wire bonding from the front surface of the MEMS array. In this article a feasibility experiment is described and successful results and process parameters are presented.

Fabrication and Performance of Silicon-Embedded Permanent-Magnet Microgenerators

This paper focuses on the design, fabrication, and characterization of silicon-packaged permanent-magnet (PM) microgenerators. The use of silicon packaging favors fine control on shape and dimensions in batch fabrication and provides a path toward high rotational speeds (1Mr/min), a requirement for ultimate compactness of microgenerators. The successful silicon packaging of these microgenerators consisted of three essential elements: (1) a winding scheme allowing both nonplanar fabrication and through-wafer interconnects; (2) laminations built into the silicon for enhanced electrical performance; and (3) a balancing scheme for the heavy PM rotor to ensure its maximum performance. The devices were fabricated using bonded silicon wafers, integrated magnetics, and an electroplated metal. The mechanical strength of the 12-mm-diameter silicon-packaged PM rotors was evaluated at high rotational speeds using an external spindle drive. Speeds up to 200000 r/min were achieved prior to a mechanical rotor failure. The generators were electrically characterized, and an output power in excess of 1 W across a resistive load of 0.32 ¿ was measured at a maximum speed. A 225% power increase was also experimentally determined due to the addition of a laminated stator back iron.

Microstructural Effects during Chemical Mechanical Planarization of Copper

Die-stacking schema using through-wafer interconnects require vias to be filled with electroplated Cu, resulting in thick copper films and requiring an aggressive first-step chemical mechanical planarization (CMP). This work investigates the effects of microstructure on CMP of copper films, which are not presently well understood. Bulk and local removal rates are investigated for several different microstructures. Surface orientation maps are created, and the orientations of individual grains are correlated with topographical data to elucidate local removal behavior. Cu removal depends on the details of the microstructure, and certain microstructures allow for either faster or more uniform removal of thick Cu films.

Parallel proximal probe arrays with vertical interconnections

This article presents the fabrication and the characteristics of 8×64, parallel, self-actuated, and independently addressable scanning proximal probes with through-silicon via interconnection passing completely through a silicon wafer. The low-resistance highly doped polysilicon through-wafer electrical interconnects have been integrated with scanning proximal probes (SPPs) to enable back side contacts to the application-specific integrated circuit used as an atomic force microscope control circuitry. Every SPP sensor contains a deflection sensor, thermally driven bimetal (bimorph) actuator, and sharp silicon tip. Dry etching-based silicon on insulator three-dimensional-micromachining technique is employed by the creation of the through-silicon vias and the SPP arrays keeping fully complementary metal-oxide semiconductor compatible process regime. The application of the vertical interconnection technology in large-scale two-dimensional cantilever arrays with off-plane bent cantilevers over the chip’s surface, in a combination with the flip-chip packaging technology allow simultaneous approach and parallel scanning of large areas in noncontact mode.

A novel capillary-effect-based solder pump structure and its potential application for through-wafer interconnection

Through-wafer electrical interconnection is a critical technology for advanced packaging. In this paper, a novel capillary-effect-based solder pump has been proposed and analyzed, which could produce interconnects through and between silicon dies. The principle of this pump is to use the surface tension of a molten solder, introduced in the form of balls, to drive sufficient material into a deep reactive-ion etched hole to form a through-wafer conductive path. The solder pump structure uses unwettable through-wafer holes of different diameters together with wettable metallization on two dies to provide the pressure differential and flow path. Using multiple feed holes and a single via hole complete through-wafer interconnects are demonstrated.

Microcantilever Probe Cards With Silicon and Nickel Composite Micromachining Technique for Wafer-Level Burn-In Testing

A new type of probe card is designed and fabricated for wafer-level integrated circuit (IC) testing. Using micromachining technology, roughly 18000 cantilever-tip probes can be integrated in one 4-in wafer, with a minimum pitch of 90 mum for adjacent probing tips. The probe card employs a silicon-and-metal composite structure, in which the bulk-micromachined silicon cantilever arrays provide uniform probing height and good planarity for the tips, as well as, the electroplated nickel probing tips feature high hardness and satisfactory electric contact with the pads to be tested. Electroplated nickel is used to simultaneously create the probing tips and the through-wafer interconnects (TWIs), which can transfer the testing signals from the dies-under-test (at the wafer bottom side) to the input/output (I/O) interface (on the front side). The probe card makes full use of the excellent mechanical properties of single-crystal silicon and satisfactory electrical properties of electroplated nickel, with the TWIs facilitating the following solder-bump flip-chip packaging. The fabricated cantilever-tip is able to withstand a contact force of 50 mN, corresponding to a tip displacement of 33 mum. The measured contact resistances on metal thin-film specimens (Al, Cu, and Au) are all below 1 Omega, whereas the maximum current leakage across two adjacent tips is 90 pA at 5 V voltage.

Reliability study of hermetic wafer level MEMS packaging with through-wafer interconnect

In this paper, we developed a hermetic wafer level packaging for MEMS devices. Au–Sn eutectic bonding technology in a relatively low temperature is used to achieve hermetic sealing, and the vertical through-hole via filled with electroplated copper for the electrical connection is also used. The MEMS package has the size of 1 mm × 1 mm × 700 μm, and a square loop Au–Sn metallization of 70 μm in width for hermetic sealing. The robustness of the package is confirmed by several tests such as shear strength test, reliability tests, and hermeticity test. The reliability issues of Au–Sn bonding technology, and copper through-wafer interconnection are discussed, and design considerations to improve the reliability are also presented. By applying O2 plasma ashing and fabrication process optimization, we can achieve the void-free structure within the bonding interface. The mechanical effects of copper through-vias are also investigated numerically and experimentally. Several factors which could induce via hole cracking failure are investigated such as thermal expansion mismatch, via etch profile, copper diffusion phenomenon, and cleaning process. Alternative electroplating process is suggested for preventing Cu diffusion and increasing the adhesion performance of the electroplating process.

Wafer-bonded 2-D CMUT arrays incorporating through-wafer trench-isolated interconnects with a supporting frame

This paper reports on wafer-bonded, fully populated 2-D capacitive micromachined ultrasonic transducer (CMUT) arrays. To date, no successful through-wafer via fabrication technique has been demonstrated that is compatible with the wafer-bonding method of making CMUT arrays. As an alternative to through-wafer vias, trench isolation with a supporting frame is incorporated into the 2-D arrays to provide through-wafer electrical connections. The CMUT arrays are built on a silicon-on-insulator (SOI) wafer, and all electrical connections to the array elements are brought to the back side of the wafer through the highly conductive silicon substrate. Neighboring array elements are separated by trenches on both the device layer and the bulk silicon. A mesh frame structure, providing mechanical support, is embedded between silicon pillars, which electrically connect to individual elements. We successfully fabricated a 16 x 16-element 2-D CMUT array using wafer bonding with a yield of 100%. Across the array, the pulse-echo amplitude distribution is uniform (rho = 6.6% of the mean amplitude). In one design, we measured a center frequency of 7.6 MHz, a peak-to-peak output pressure of 2.9 MPa at the transducer surface, and a 3-dB fractional bandwidth of 95%. Volumetric ultrasound imaging was demonstrated by chip-to-chip bonding one of the fabricated 2-D arrays to a custom-designed integrated circuit (IC). This study shows that through-wafer trench-isolation with a supporting frame is a viable solution for providing electrical interconnects to CMUT elements and that 2-D arrays fabricated using waferbonding deliver good performance.