Through-wafer Interconnects Research Articles

Photoresist coating and patterning for through-silicon via technology

Three-dimensional (3D) integration requires through-wafer interconnects, i.e. an integration of electrical connections from one side of the wafer to the other side. In some cases, it involves the lithographic patterning of through-Si via (TSV). For this step, a conformal coating of a resist layer is necessary. In this paper, we present two potential photoresist coating methods for coating a wafer with TSV: spray coating and electrodeposition (ED) of the photoresist. Lithographic patterning inside the TSV is also investigated. Some parameters that influence the pattern definition, such as large gap exposure, resist thickness and via size, are identified and evaluated.

A metallic buried interconnect process for through-wafer interconnection

In this paper, we present the design, fabrication process and experimental results of electroplated metal interconnects buried at the bottom of deep silicon trenches with vertical sidewalls. A manual spray-coating process along with a unique trench-formation process has been developed for the electroplating of a metal interconnection structure at the bottom surface of the deep trenches. The silicon etch process combines the isotropic dry etch process and conventional Bosch process to fabricate a deep trench with angled top-side edges and vertical sidewalls. The resulting trench structure, in contrast to the trenches fabricated by wet anisotropic etching, enables spray-coated photoresist patterning with good sidewall and top-side edge coverage while maintaining the ability to form a high-density array of deep trenches without excessive widening of the trench opening. A photoresist spray-coating process was developed and optimized for the formation of electroplating mold at the bottom of 300 µm deep trenches having vertical sidewalls. A diluted positive tone photoresist with relatively high solid content and multiple coating with baking between coating steps has been experimentally proven to provide high quality sidewall and edge coverage. To validate the buried interconnect approach, a three-dimensional daisy chain structure having a buried interconnect as the bottom connector and traces on the wafer surface as the top conductor has been designed and fabricated.

The fabrication of through-wafer interconnects in silicon substrates for ultra-high-vacuum atom-optics cells

This paper describes a new method for fabricating through-wafer interconnects in atom trapping chips used in ultra-high-vacuum atom-optics cells for Bose–Einstein condensation (BEC) experiments. A fabrication process was developed which uses copper electroplating to seal the vias. The advantages of using feedthrough atom trapping chips are the simple microfabrication process and the reduction of the overall chip area bonded to the glass atom trapping cell. The results demonstrate that 11 A current can be conducted through the vias while the vacuum can be held under 4 × 10−11 Torr at room temperature. The yield rate of fabricated via interconnects in this process after anodic bonding (requires heating to 425 °C) is 97%.

Integrating Through-Wafer Interconnects With Active Devices and Circuits

Through wafer interconnects (TWIs) enable vertical stacking of integrated circuit chips in a single package. A complete process to fabricate TWIs has been developed and demonstrated using blank test wafers. The next step in integrating this technology into 3D microelectronic packaging is the demonstration of TWIs on wafers with preexisting microcircuitry. The circuitry must be electrically accessible from the backside of the wafer utilizing the TWIs; the electrical performance of the circuitry must be unchanged as a result of the TWI processing; and the processing must be as cost effective as possible. With these three goals in mind, several options for creating TWIs were considered. This paper explores the various processing options and describes in detail, the final process flow that was selected for testing, the accompanying masks that were designed, the actual processing of the wafers, and the electrical test results.

Integration of 2D CMUT arrays with front-end electronics for volumetric ultrasound imaging

For three-dimensional (3D) ultrasound imaging, connecting elements of a two-dimensional (2D) transducer array to the imaging system's front-end electronics is a challenge because of the large number of array elements and the small element size. To compactly connect the transducer array with electronics, we flip-chip bond a 2D 16 x 16-element capacitive micromachined ultrasonic transducer (CMUT) array to a custom-designed integrated circuit (IC). Through-wafer interconnects are used to connect the CMUT elements on the top side of the array with flip-chip bond pads on the back side. The IC provides a 25-V pulser and a transimpedance preamplifier to each element of the array. For each of three characterized devices, the element yield is excellent (99 to 100% of the elements are functional). Center frequencies range from 2.6 MHz to 5.1 MHz. For pulse echo operation, the average - 6-dB fractional bandwidth is as high as 125%. Transmit pressures normalized to the face of the transducer are as high as 339 kPa and input-referred receiver noise is typically 1.2 to 2.1 mPa/pHz. The flip-chip bonded devices were used to acquire 3D synthetic aperture images of a wire-target phantom. Combining the transducer array and IC, as shown in this paper, allows for better utilization of large arrays, improves receive sensitivity, and may lead to new imaging techniques that depend on transducer arrays that are closely coupled to IC electronics.

RF–MEMS wafer-level packaging using through-wafer interconnect

In this paper, development of a wafer-level packaging (WLP) process suitable for RF–MEMS applications is presented. The packaging concept is based on a high-resistivity silicon capping substrate that is wafer-level bonded to an RF–MEMS device wafer providing MEMS device protection and vertical electrical signal interconnect. The capping substrate contains Cu-plated through-wafer electrical vias and optional through-substrate cavities allowing for hybrid integration. The RF–MEMS device wafer and the capping substrate are bonded using either solder reflow or an electrically conductive adhesive. After solder bump formation and singulation, this packaging solution results in surface-mount technology compatible components. Moreover, the presented WLP solution allows hybrid integration of additional IC dies that are flip-chip bonded within the capping substrate cavities.

Aligned carbon nanotubes for through-wafer interconnects

Through-wafer interconnects by aligned carbon nanotube for three-dimensional stack integrated chip packaging applications have been reported in this letter. Two silicon wafers are bonded together by tetra-ethyl-ortho-silicate. The top wafer (100μm thick) with patterned through-holes allows carbon nanotubes to grow vertically from the catalyst layer (Fe) on the bottom wafer. By using thermal chemical vapor deposition technique, the authors have demonstrated the capability of growing aligned carbon nanotube bundles with an average length of 140μm and a diameter of 30μm from the through holes. The resistivity of the bundles is measured to be 0.0097Ωcm by using a nanomanipulator.

Fully tileable photodiode matrix for medical imaging by using through-wafer interconnects

This paper presents a technology for a fully tileable two-dimensional (2D) photodiode matrix for medical imaging, specifically X-ray computed tomography (CT). A key trend in the CT industry is to build machines with larger area detector to speed up the measurements and to avoid image blurring due to patient movement during scanning. In current CT detector constructions, a major limiting factor in providing more detector coverage is the need to read out the signals from the individual photo-detector elements of the detector array through lines along the surface facing the radiation source and wire bonds down to a substrate or to an electronics chip. Using this method, there is a physical limitation on the size of a photo-detector array that may be manufactured. A photo-detector with the possibility of expansion in all directions is known as a ‘tileable’ detector. A technology of integrating through-wafer interconnects (TWIs) with traditional front illuminated photodiodes is introduced. Photocurrent can be read out from back side of the photodiode chip through interconnects, giving possibility of constructing arbitrarily large area of photo-detector for CT machine. Results of a sample 2D demonstrator detector array are presented showing that the requirements of modern CT systems can be met.

Implementation of three-dimensional SOI-MEMS wafer-level packaging using through-wafer interconnections

Packaging is an emerging technology for microsystem integration. The silicon-on-insulator (SOI) wafer has been extensively employed for micromachined devices for its reliable fabrication steps and robust structures. This research reports a packaging approach for silicon-on- insulator-micro-electro-mechanical system (SOI-MEMS) devices using through-wafer vias and anodic bonding technologies. Through-wafer vias are embedded inside the SOI wafers, and are realized using laser drilling and electroplating. These vias provide electrical signal paths to the MEMS device, while isolating MEMS devices from the outer environment. A high-strength hermetic sealing is then achieved after anodic bonding of the through-wafer-vias-embedded SOI wafer to a Pyrex 7740 glass. Moreover, the packaged SOI-MEMS chip is compatible with surface mount technology, and provides a superior way for 3D heterogeneous integration.

Integration of trench-isolated through-wafer interconnects with 2d capacitive micromachined ultrasonic transducer arrays

This paper presents a method to provide electrical connection to a 2D capacitive micromachined ultrasonic transducer (CMUT) array. The interconnects are processed after the CMUTs are fabricated on the front side of a silicon wafer. Connections to array elements are made from the back side of the substrate via highly conductive silicon pillars that result from a deep reactive ion etching (DRIE) process. Flip-chip bonding is used to integrate the CMUT array with an integrated circuit (IC) that comprises the front-end circuits for the transducer and provides mechanical support for the trench-isolated array elements. Design, fabrication process and characterization results are presented. The advantages when compared to other through-wafer interconnect techniques are discussed.

Fabrication of silicon based through-wafer interconnects for advanced chip scale packaging

This paper presents a fabrication method to achieve through-wafer interconnects (TWIs) by etching, filling and grinding in sequence. Based on this method, advanced chip scale packaging (CSP) is performed. Compared to flip-chip technology, silicon based sensors or actuators, especially large scale detector arrays, can be assembled into a system with the sensing surface upwards, and electrical signals can then be extracted from the back side of the chip without sacrificing the front sensing surface by using TWIs. In addition, it also makes 3-D chip stacking possible. Generally speaking, less than 1.5 pF capacitance and 240 Ω resistance are measured from the fabricated wafer. In order to better integrate the TWIs into different sensor systems, the ability to vary the capacitance of the TWIs is discussed based on a metal-oxide-semiconductor (MOS) model. From leakage current simulation results, possible defects during the processing of TWIs are addressed and detected by introducing different failure mechanisms of the insulation of the TWIs. As a result, the fabrication of TWIs and their related CSP procedure have proved that it is a promising technology for a range of sensor applications.

Experimental Studies of Through-Wafer Copper Interconnect in Wafer Level MEMS Packaging

In this paper, mechanical reliability issues of copper through-wafer interconnection are investigated numerically and experimentally. Several factors which could induce via hole cracking failure are investigated such as thermal expansion mismatch, via etch profile, copper diffusion phenomenon, and cleaning process. Improvement methods are also suggested.

Chip-Scale Integration of Data-Gathering Microsystems

Integrated microsystems merging embedded computing with sensing and actuation are poised to dramatically expand our ability to gather information from the nonelectronic world. Examples include a microassembled multichip electronic interface to the brain, an integrated electrofluidic gas chromatography system for environmental monitoring, and a wireless intra-arterial microsystem for pressure and flow measurements. In general, such microsystems will consist of a few chips, integrated in generic platforms that are customized for a given application by the sensors selected and by software. This paper illustrates this approach with a 0.15-cm/sup 3/ multisensor microsystem for autonomously sensing and storing environmental and biological data. The microsystem is formed using on-board pressure/temperature/humidity sensors, off-board strain gauges and neural/EMG electrodes, a custom sensor-interface chip, a mixed-signal microcontroller, and a nonvolatile memory. These components allow the acquisition and storage of multidomain data at low power levels (< 50 /spl mu/W reading capacitive sensors at 1 Hz). The system is programmable in gain (0.4-3.2 mV/fF), offset (10b), accuracy (14b), and sampling rate (0.1 Hz-10 kHz) and is integrated in a micromachined silicon platform that implements through-wafer interconnects, solder-based microconnectors, and recessed cavities for chip-stacking. The microsystem is realized in 9.5 mm/spl times/7.6 mm/spl times/2.0 mm (0.15 cm/sup 3/) (< 0.5 cm/sup 3/ with a lithium battery).

Development of cost-effective high-density through-wafer interconnects for 3D microsystems

High-density through-wafer interconnects are of great interest for fabricating real 3D microsystems. A complete solution for realizing through-wafer interconnects is presented. The proposed solution is believed to be cost effective and easy to integrate in a device process flow. A deep reactive ion etch process was developed to etch 20 × 20 µm2 via holes through 300 µm thick silicon wafers. Thermal oxide is used to insulate the vias from the bulk silicon and heavily doped polysilicon is used as the conductor. Aluminum metallization is provided on both sides of the wafer. The electrical resistance of a single through-wafer via is close to 30 Ω.

Aspect-Ratio-Dependent Copper Electrodeposition Technique for Very High Aspect-Ratio Through-Hole Plating

Copper electrodeposition in high-aspect-ratio through-holes micromachined by deep reactive ion etching is one of the most essential processes for fabricating through-wafer interconnects, which will be used in developing future generation high-speed, compact 3D microelectronic devices. Although copper electrodeposition is a well-established process, completely void-free electroplating in very deep and narrow through-holes remains a challenge, where local current distribution does not remain uniform, resulting in void formation in the via. In this paper, we report the fabrication of very high aspect ratio through-wafer copper interconnects by an innovative copper electroplating technique. Completely void-free electroplating in very deep and narrow through-holes was accomplished by a proposed “aspect-ratio-dependent electroplating technique.” In this technique, electroplating parameters were continuously varied along with changing unfilled via depth. Continuously varying current density improves the local distribution of current as per the changing depth and helps in minimizing void formation. The hydrophilic nature of the via surface was also enhanced by wet surface treatment to improve the interaction between the copper electrolyte and via surface. Very fine pitch , through-wafer copper interconnects having an aspect ratio as high as 15 were fabricated by the above innovative technique.

Through Wafer Interconnects - A Technology not only for Medical Applications

AbstractThe foremost driver for the development of fully CMOS compatible Through Wafer Interconnects (TWIs) is the need of very large photodiode arrays for detectors, e.g. in computed tomography applications. The front to back-side contact allows the four-side buttable chip placement of the already large chips (20mm × 22mm2). The TWI technology allows an interconnection for chips up to 280μm thickness. This technique does not require any via opening at the font side, thus enabling a metal signal routing on the active side, on top of the interconnection. The application specific optical sensitive front-side of the chip is fully accessible. The production process is separated into three main steps. The first step is the implementation of the special TWI geometry into the CMOS substrate. Depending on the electrical and geometrical requirements of the circuit, different TWI structures are built with deep trenches (up to 280μm), which are passivated and filled with doped poly-silicon. The technologies used in this process, such as DRIE-etching, oxidation and low pressure CVD, are standard CMOS compatible processes. The use of poly-silicon prevents from achieving very low resistivity interconnections but allows the use of all CMOS process steps for an imager production (no temperature limitation – compared to other TWI process flows). The second step is the standard CMOS processing on the substrate already including the TWIs. The third step is a low temperature back-side process starting with wafer thinning down to 280μm or less to open the implemented TWI structure from the back-side. The thickness may be selected depending on the target application. A modified under ball metallization (UBM) process, which could include also re-routing of signals on the back-side, concludes the process flow until the solder ball placement, or similar bond connections.The special process flow opens a variety of applications which benefit from the full CMOS compatible processing and the accessible front-side.

Through Wafer Interconnects - A Technology not only for Medical Applications

AbstractThe foremost driver for the development of fully CMOS compatible Through Wafer Interconnects (TWIs) is the need of very large photodiode arrays for detectors, e.g. in computed tomography applications. The front to back-side contact allows the four-side buttable chip placement of the already large chips (20mm × 22mm2). The TWI technology allows an interconnection for chips up to 280μm thickness. This technique does not require any via opening at the font side, thus enabling a metal signal routing on the active side, on top of the interconnection. The application specific optical sensitive front-side of the chip is fully accessible. The production process is separated into three main steps. The first step is the implementation of the special TWI geometry into the CMOS substrate. Depending on the electrical and geometrical requirements of the circuit, different TWI structures are built with deep trenches (up to 280μm), which are passivated and filled with doped poly-silicon. The technologies used in this process, such as DRIE-etching, oxidation and low pressure CVD, are standard CMOS compatible processes. The use of poly-silicon prevents from achieving very low resistivity interconnections but allows the use of all CMOS process steps for an imager production (no temperature limitation – compared to other TWI process flows). The second step is the standard CMOS processing on the substrate already including the TWIs. The third step is a low temperature back-side process starting with wafer thinning down to 280μm or less to open the implemented TWI structure from the back-side. The thickness may be selected depending on the target application. A modified under ball metallization (UBM) process, which could include also re-routing of signals on the back-side, concludes the process flow until the solder ball placement, or similar bond connections.The special process flow opens a variety of applications which benefit from the full CMOS compatible processing and the accessible front-side.

Microwave characterization and modeling of high aspect ratio through-wafer interconnect vias in silicon substrates

In this paper, we present the detailed fabrication process, high-frequency characterization, and modeling of through-wafer copper-filled vias ranging from 50- to 70-/spl mu/m-in diameter on 400-/spl mu/m-thick silicon substrates. The high aspect ratio via-holes were fabricated by carefully optimizing the inductively coupled plasma deep reactive ion etching process. The high aspect ratio via-holes are completely filled with copper using a bottom-up electroplating approach. The fabricated vias were characterized using different resonating structures based on which the inductance and resistance of the filled via-holes are extracted. For a single 70-/spl mu/m via, the inductance and resistance are measured to be 254 pH and 0.1 /spl Omega/, respectively. In addition, the effect of the physical arrangement and distribution in multiple-via configurations on the resulting inductance is also evaluated with double straightly aligned quadruple and diagonally aligned quadruple vias. Physical mechanisms of the dependence was depicted by electromagnetic simulation. An equivalent-circuit model is proposed and model parameters are extracted to provide good agreement.

Through-Wafer Polysilicon Interconnect Fabrication with In-Situ Boron Doping

AbstractBulk micromachining technology can be used to produce conducting through-wafer polysilicon interconnects, i.e., polysilicon via plugs. This paper presents the process fabrication steps of polysilicon via plugs with in-situ boron doped polysilicon material in order to develop fast one-step doping process, without additional diffusion. The via holes can be processed by high-aspect ratio silicon etching with inductively coupled plasma (ICP). Only one deep ICP etching is required if the wafer is mechanically ground (from the backside) to reduce the wafer thickness of 500 microns to a typical of 400, in order to overcome deep etching sidewall profile problems. After hole formation with ICP the via plug fabrication process continues by growing an insulating thermal oxide layer with a thickness of the order of a micron, followed by an in-situ boron doped LPCVD polysilicon growth to fill the holes with sufficient step coverage. The polysilicon growth temperature at 680°C ensures sufficient step coverage, reasonable furnace process time and enables planarization processing, such as grinding and chemical-mechanical polishing (CMP). The subsequent planar processing typically requires planarization of the polysilicon layer down to the original silicon (or oxide) surface with CMP, and some doping activation step, which usually can be performed together with some additional oxidation step. Applications of the via plugs in the field of silicon-based sensors or actuators enable significant reduction of the front surface wiring density, which opens additional space for denser packing or other desired components.

A Through-Wafer Interconnect in Silicon for RFICs

In order to minimize ground inductance in RFICs, we have developed a high-aspect ratio, through-wafer interconnect (or substrate via) in silicon that features a silicon nitride barrier liner and completely filled Cu core. We have fabricated vias with a nominal aspect ratio of 30 and verified the integrity of the insulating liner in vias with an aspect ratio of eight. The inductance of vias with nominal aspect ratios between three and 30 approach the theoretically expected values. This interconnect technology was exploited in a novel Faraday cage structure for substrate crosstalk suppression in system-on-chip applications. The isolation structure consists of a ring of grounded vias that surrounds sensitive or noisy portions of a chip. This Faraday cage structure has shown noise suppression of 30 dB at 10 GHz and 16 dB at 50 GHz at a distance of 100 /spl mu/m when compared to the reference structure.