Through Silicon Via Depth Research Articles

Integrated MEMS Toroidal Transformer With Ni-Zn Ferrite Core for Power Supply on Chip

A miniature integrable transformer is an obstacle to the miniaturization of packaged power supply on chip (PwrSoC). This letter introduces a through-silicon via (TSV) high-aspect-ratio toroidal transformer manufactured using microelectro-mechanical systems and electroplating. The primary coil and secondary coil of the transformer are interleaved on the toroidal core cavity, which is entirely wrapped in silicon, and a 1.2 mm high toroidal Ni-Zn ferrite core is formed. A 15:15 turn transformer is fabricated with a compact coil size of Φ4.1 × 2 mm with an aspect ratio (ratio of TSV depth to diameter) of 20. Measurements show that it has an inductance of 105 to 115 nH in a high frequency range of 1 to 80 MHz and a coupling coefficient of ∼0.7 in the range of 1 MHz to >15 MHz. Compared to that of the transformer without the Ni-Zn ferrite core, the coupling coefficient of the toroidal transformer increases by 40% with an inductance increase of 20%. At a frequency of 14 MHz, the transformer has a maximum quality factor of 16.7. The small size, IC compatible manufacturing process and excellent performance at high-frequency of the transformer proposed, meet the further integrated and miniaturized needs of PwrSoC.

Development of a high-yield via-last through silicon via process using notchless silicon etching and wet cleaning of the first metal layer

A high-yield via-last through silicon via (TSV) process has been developed using notchless Si etching and wet cleaning of the first metal layer. In this process, the notching was suppressed by optimizing the deep Si etching conditions and wet cleaning was performed using an organic alkaline solution to remove reaction products generated by the etchback step on the first metal layer. By this process, a number of small TSVs (TSV diameter: 6 µm; TSV depth: 22 µm; number of TSVs: 20,000/chip) could be formed uniformly on an 8-in. wafer. The electrical characteristics of small TSVs formed by this via-last TSV process were investigated. The TSV resistance determined by four-terminal measurements was approximately 24 mΩ. The leakage current between the TSV and the Si substrate was 2.5 pA at 5 V. The TSV capacitance determined using an inductance–capacitance–resistance (LCR) meter was 54 fF, while the TSV yield determined from TSV chain measurements was high (83%) over an 8-in. wafer.

Development of TSV Reveal Process Using Very Fine Si/Cu Grinding and Metal Contamination Removal

Three-dimensional integrated circuits (3D-ICs) using through silicon via (TSV) have been developed as an emerging technology that can lead to significant progress (1–4). Among various TSV processes, the via-middle process has potential for wide spread use because formation of small-sized TSVs is relatively easy in the via-middle process. However, TSV reveal process must be performed for electrical contact in the via-middle process. This TSV reveal process is important because it can influence the metal contamination and stacking yield of 3D-ICs. Conventionally, TSV reveal is performed by Si grinding and Si dry etching (5). A disadvantage of that method is the resultant TSV depth deviation, which can cause bonding failure during wafer/chip stacking. In (6), TSV leveling was performed by introducing a chemical mechanical polishing (CMP) step after deposition of the backside insulator. However, the revealed TSVs break during CMP step if they exceed a certain height. To overcome these problems, we developed a novel TSV reveal process comprising direct Si/Cu grinding and metal contamination removal (7,8). First, simultaneous grinding of Cu and Si was performed using a novel vitrified grinding wheel. In situ cleaning with a high-pressure micro jet and the inelastic porous structure of the grinding wheel suppressed the adhesion of Cu contaminants to the Si, and TSVs were leveled and exposed. Next, an electroless Ni-B film was deposited on the Cu surface of the TSVs. The Si was etched with an alkaline solution, whereas the Cu was protected by the Ni-B film. An insulator was deposited, and then the insulator on the top surface of the TSV was removed. We achieved the backside reveal of TSVs without TSV depth deviation and suppressed Cu contamination to less than 1e11 atoms/cm2. However, after direct Si/Cu grinding with an 8000 grit grinding wheel, the average surface roughness of Si was 5–10 nm, which is larger than that after chemical mechanical polishing (CMP). In this paper, we developed vitrified grinding wheels with very high grit numbers (#30,000 and #45,000) and present an improved version of our TSV reveal process. The average surface roughness of Si after Si/Cu grinding was approximately 3 nm for the 30,000 grit grinding wheel and 1 nm for the 45,000 grit grinding wheel. This value is equivalent to that after CMP. The improved process produced a uniform reveal of 4-um-diameter TSVs without TSV depth deviation and Cu contamination. The Cu contaminant concentration on Si region between TSVs was small (<3e10 atoms/cm2). This process will reduce the cost of the TSV reveal process and considerably improve the TSV yield.

In-line through silicon vias etching depths inspection by spectroscopic reflectometry

Through-silicon via (TSV) technology is a key feature for 3D circuit integration. The nondestructive metrology of deep-etched structures with aspect ratio of >10 and patterns with lateral dimensions in the range up to 5μm remains an challenge and can be overcome by destructive control. In this paper the inspection of TSV depth and critical dimensions (CD) of their opening were performed nondestructively by an industrial thickness measurement tool (UV–VIS spectral reflectometer). The possibilities and limits of in-line optical tools for the characterization of the high density TSV array of high aspect-ratio square vias with tapered profile in Si were examined. TSV with CD from 3 up to 7μm, pitch in the range of 7–11μm, and etch depth of 50–70μm were investigated. The TSV depth was determined using the interference effect between reflected waves from the top and bottom surfaces of the TSV structures. The rigorous coupled wave analysis (RCWA) is successfully applied to the analysis of the spectral reflectance for the determination of the TSV top and bottom CD and profile evaluation. It was shown that this method can be used for the monitoring of geometrical parameters of TSVs with dimensions from 3μm and aspect ratios up to 17:1. The non-destructive measurement data provide excellent correlation with SEM results.

Energy Release Rate Estimation for Through Silicon Vias in 3-D IC Integration

The technology of 3-D IC integration is expected to satisfy the demand for high-performance, better reliability, miniaturization, and lower priced portable electronic products. Since through silicon via (TSV) is at the heart of 3-D IC integration architectures, the reliability issues with TSV interconnects are an area of extreme concern. Due to the large thermal expansion mismatch among the copper (Cu), silicon die, and silicon dioxide (SiO2) dielectric layer, the induced thermal stresses and strains can occur and become the driving forces that cause failures in TSV interconnects. Hence, thermomechanical stress analyses and failure mode investigations for TSVs are in urgent need. Among the typical failures, delamination is the mostly common failure type, which is caused when lower energy release rate (ERR) or higher critical stresses at interfaces are present. In this paper, the finite element analysis (FEA) for a symmetrical single inline Cu-filled TSV with redistribution layer is illustrated and has been used to realize the thermomechanical stress distribution for TSVs in 3-D IC integration. Moreover, four kinds of interfacial cracks that were embedded in the interface of SiO2 passivation and Cu seed layer (Cu pad and TSV wall delamination cases) and the critical stress areas observed from FEA are introduced to estimate the interfacial ERR using modified virtual crack closure technique. The parametric study has also been adopted to capture the most important mechanical factors of the TSVs to comprehend the corresponding ERR. The significance of discussed parameters such as crack length, TSV diameter, TSV pitch, TSV depth, SiO2 thickness, and Cu seed layer thickness are also examined. It is believed that these results would be helpful to avoid delamination of TSV interconnects in 3-D IC integration.

Development of Wafer-Level Warpage and Stress Modeling Methodology and Its Application in Process Optimization for TSV Wafers

Through-silicon via (TSV) technology has been widely investigated recently for 3-D electronic packaging integration. Reducing TSV wafer warpage is one of the most challenging concerns for successfully subsequent processes. In this paper, a wafer-level warpage modeling methodology has been developed by the finite element analysis method using an equivalent material model. The developed modeling methodology has been verified by numerical results and experimental data. Using the developed model, wafer warpage has been simulated and analyzed by considering different factors, such as annealing temperature, copper (Cu) overburden thickness, TSV depth, and diameter. Simulation results show that wafer warpage increases with increasing annealing temperature and Cu overburden thickness. Such findings have been successfully used in TSV process optimization to reduce wafer warpage after annealing process. A global-local modeling methodology has also been implemented to determine wafer stress accurately. Wafer bending stress is high at wafer surface and close to TSV edge. Wafer bending stress increases with increasing TSV diameter and it is higher at the edge of TSVs with finer pitch.

Influence of Bosch Etch Process on Electrical Isolation of TSV Structures

Bosch process is widely used in the fabrication of through silicon via (TSV) holes for 3-D integrated circuit and 3-D Packaging applications mainly due to its high silicon etch rate and selectivity to mask. However, the adverse impact on the electrical performance of the TSV due to the sidewall scallops or wavy profile due to the cyclical nature of the Bosch process has not been thoroughly investigated. This paper therefore focuses on the impact of sidewall scallops on the inter-via electrical leakage performance. Based on finite element analysis, this paper describes that the high stress concentration on the dielectric and barrier layers at the sharp scallops can potentially contribute to barrier failure. It is demonstrated that by smoothening the sidewalls of the TSV, the thermo-mechanical stresses on the dielectric and tantalum barrier is significantly reduced. A test vehicle is designed and fabricated with different geometry of deep silicon vias to study the impact of sidewall profile smoothening for different copper diffusion barrier stacks. It is experimentally demonstrated that the inter-via electrical leakage current can be reduced by almost three orders of magnitude when the sidewall roughness is reduced or replaced by a smoother sidewall. It is also indicated that it is sufficient to smoothen the initial few micrometers of the TSV depth by using a non-Bosch etch process. It is concluded that the Bosch etch process can still be used, with all its merits of high etch rate and high etch selectivity, by tailoring a short initial etch step to smoothen the top sidewalls to minimize the adverse effects of the sidewall scallops.

Backside Infrared Interferometric Patterned Wafer Thickness Sensing for Through-Silicon-Via (TSV) Etch Metrology

A quantitative metrology technique is required to provide quality control necessary for production-worthy through-silicon-via (TSV) etch. This paper reports on backside infrared interferometric wafer thickness sensing for highly repeatable, nondestructive, and high-throughput determination of TSV depth, unlimited by aspect ratio (AR). Selected etch depth measurements for 1-18 μm critical dimension TSVs with AR up to 28:1 are demonstrated with 3 sigma measurement repeatability of less than 50 nm. On the 5 μm×25 μm TSV etch process baseline on 300 mm wafers, lot-to-lot, run-to-run, and within wafer etch depth variations have been quantified in a production-worthy fashion. This technique has found no appreciable depth differences between dense and isolated TSVs within run, and has identified improvements in run-to-run variability when using oxide conditioning wafers.

300-mm Production-Worthy Magnetically Enhanced Non-Bosch Through-Si-Via Etch for 3-D Logic Integration

We report a process development route toward 300-mm production-worthy non-Bosch through-silicon-via (TSV) etch with critical dimensions between 1-5 ?m and aspect ratios up to 20:1 for 3-D logic applications. The etch development was performed on an experimental alpha-tool: a magnetically enhanced capacitively coupled plasma etcher with a dipole ring magnet that aims to capture the strengths (anisotropicity, profile uniformity) while eliminating the weaknesses (scalloping, undercut, residues) of a nominal Bosch process. Key factors contributing to the control of sidewall taper and roughness, etched TSV volume and depth, mask undercut, local bowing effects, and within wafer (WIW) center-to-edge depth and profile uniformity were evaluated. TSVs with nominal sizes of 5 × 25 ?m, 5 × 40 ?m and 1 × 20 ?m with less than 1% WIW nonuniformity, negligible silicon scalloping/mask undercut, and good profile anisotropicity were developed. Up to 3 × 20 ?m and 5 × 25 ?m void-free Cu-filled TSVs were demonstrated with both vertical TSVs and tapered TSVs.