Energy Release Rate Estimation for Through Silicon Vias in 3-D IC Integration

Abstract

The technology of 3-D IC integration is expected to satisfy the demand for high-performance, better reliability, miniaturization, and lower priced portable electronic products. Since through silicon via (TSV) is at the heart of 3-D IC integration architectures, the reliability issues with TSV interconnects are an area of extreme concern. Due to the large thermal expansion mismatch among the copper (Cu), silicon die, and silicon dioxide (SiO2) dielectric layer, the induced thermal stresses and strains can occur and become the driving forces that cause failures in TSV interconnects. Hence, thermomechanical stress analyses and failure mode investigations for TSVs are in urgent need. Among the typical failures, delamination is the mostly common failure type, which is caused when lower energy release rate (ERR) or higher critical stresses at interfaces are present. In this paper, the finite element analysis (FEA) for a symmetrical single inline Cu-filled TSV with redistribution layer is illustrated and has been used to realize the thermomechanical stress distribution for TSVs in 3-D IC integration. Moreover, four kinds of interfacial cracks that were embedded in the interface of SiO2 passivation and Cu seed layer (Cu pad and TSV wall delamination cases) and the critical stress areas observed from FEA are introduced to estimate the interfacial ERR using modified virtual crack closure technique. The parametric study has also been adopted to capture the most important mechanical factors of the TSVs to comprehend the corresponding ERR. The significance of discussed parameters such as crack length, TSV diameter, TSV pitch, TSV depth, SiO2 thickness, and Cu seed layer thickness are also examined. It is believed that these results would be helpful to avoid delamination of TSV interconnects in 3-D IC integration.