through-Si Vias Research Articles

(Invited) Electrochemical Deposition for Applications in the Semiconductor Industry

This year (2023) marks the 25th anniversary of the “Damascene copper electroplating for chip interconnections” publication by P.C. Andricacos et al [1] detailing the dual-damascene process and Cu superfilling of complex structures. And even though this was neither the only electrochemistry contribution to the semiconductor industry nor the first time to report successful plating of Cu structures, it signaled that electrochemical deposition would play prominent role in downscaling race [2]. The authors described Cu superfilling of a feature having characteristic dimensions of about 1 micron. Since then, electrochemists have focused intensely on electrolyte development, optimization of deposition parameters, and improvements in plating tools and process chambers, which went hand in hand with downscaling of features to be filled. Cu was plated on resistive substrates and alternative seeds, various surface pretreatments were applied, and nucleation and growth phenomena studied [3-6], until the focus shifted to alternative metals, such as Co [7]. While Chemical vapor deposition (CVD) and Atomic layer deposition (ALD) offer viable alternatives to electrochemical deposition (ECD) in fabrication of interconnects having width of several nanometers, new challenges and opportunities in 3D packaging and stacking appeared on the horizon. This field resembles more a ‘landscape’ than a ‘one-way street’ that damascene nano-interconnects were. While on one hand downscaling is gaining momentum here, too, there is also upscaling. For example, electrochemically deposited mega-pillars have diameters and heights exceeding hundreds of microns. More than a decade ago, a competitive race started between chemistry suppliers, tool manufacturers and scientists in the field to achieve bottom-up Cu fill of through-Si-vias (TSV) [8], structures meant to provide interconnections between vertically stacked integrated circuits. These structures had characteristic sizes an order of magnitude larger than the ones described in [1]. After demonstrating that superfilling of TSV was indeed possible, it became imperative to satisfy a plethora of production-line requirements, such as optimization of plating time or control of the so-called Cu pumping, a plastic deformation of Cu upon annealing. Plastic deformation leads to an uneven top surface and challenges in stacking layers on top of each other and is, therefore, undesirable. Today, researchers are contemplating possible benefits of the plastic deformation in Cu structures to establish a more robust and reliable Cu-to-Cu bonding process. Achieving defect-free fill of features was never the only requirement to be satisfied, but the ability to control plastic deformation in Cu features, or fabricate structures with specific texture, grain size, crystal structure [9, 10] on sub-micron scale, might require more thorough modifications of the current Cu plating processes. We will review this and other current trends in electrochemical deposition for applications in ‘classical’ semiconductor industry. We will also consider possibilities in technologies for Quantum computing, where a new spectrum of non-traditional candidate elements for plating could emerge [11, 12]. There, lessons learned from the downscaling of traditional interconnects could prove very useful.

Advanced 3D Through-Si-Via and Solder Bumping Technology: A Review.

Three-dimensional (3D) packaging using through-Si-via (TSV) is a key technique for achieving high-density integration, high-speed connectivity, and for downsizing of electronic devices. This paper describes recent developments in TSV fabrication and bonding methods in advanced 3D electronic packaging. In particular, the authors have overviewed the recent progress in the fabrication of TSV, various etching and functional layers, and conductive filling of TSVs, as well as bonding materials such as low-temperature nano-modified solders, transient liquid phase (TLP) bonding, Cu pillars, composite hybrids, and bump-free bonding, as well as the role of emerging high entropy alloy (HEA) solders in 3D microelectronic packaging. This paper serves as a guideline enumerating the current developments in 3D packaging that allow Si semiconductors to deliver improved performance and power efficiency.

Reduction of Metal/Carbon Nano-Tubes Interface Contact Resistance by Floating Catalyst Growing Method and Semimetals

In this work, we investigate the contact resistance between carbon nanotubes (CNTs) and different metal electrodes (In, Cr, Cu, Ni, W, and Bi) grown by two methods: floating catalyst chemical vapor deposition (FCCVD) and thin Fe metal chemical vapor deposition (CVD). The results demonstrate that CNTs grown by FCCVD have lower contact resistance with metal electrodes compared to those grown by thin Fe metal CVD. The study attributes this to the avoidance of metal-silicide formation between the silicon (Si) substrate and the metal catalyst film during the high-temperature growing process in FCCVD. Moreover, the research shows that the FCCVD method results in a higher CNT density grown in the through Si vias (TSVs) and lower contact resistance between metal electrodes and CNTs, moving toward the 3-D integrated circuits (3-DICs). Further, the use of metals with good wettability such as bismuth (Bi) as the metal electrode reduces contact resistance.

Tunable MEMS-Based Terahertz Metamaterial for Pressure Sensing Application.

In this study, a tunable terahertz (THz) metamaterial using the micro-electro-mechanical system (MEMS) technique is proposed to demonstrate pressure sensing application. This MEMS-based tunable metamaterial (MTM) structure is composed of gold (Au) split-ring resonators (SRRs) on patterned silicon (Si) substrate with through Si via (TSV). SRR is designed as a cantilever on the TSV structure. When the airflow passes through the TSV from bottom to up and then bends the SRR cantilever, the SRR cantilever will bend upward. The electromagnetic responses of MTM show the tunability and polarization-dependent characteristics by bending the SRR cantilever. The resonances can both be blue-shifted from 0.721 THz to 0.796 THz with a tuning range of 0.075 THz in transverse magnetic (TM) mode and from 0.805 THz to 0.945 THz with a tuning range of 0.140 THz in transverse electric (TE) mode by changing the angle of SRR cantilever from 10° to 45°. These results provide the potential applications and possibilities of MTM design for use in pressure and flow rate sensors.

A Review on the Fabrication and Reliability of Three-Dimensional Integration Technologies for Microelectronic Packaging: Through-Si-via and Solder Bumping Process

With the continuous miniaturization of electronic devices and the upcoming new technologies such as Artificial Intelligence (AI), Internet of Things (IoT), fifth-generation cellular networks (5G), etc., the electronics industry is achieving high-speed, high-performance, and high-density electronic packaging. Three-dimensional (3D) Si-chip stacking using through-Si-via (TSV) and solder bumping processes are the key interconnection technologies that satisfy the former requirements and receive the most attention from the electronic industries. This review mainly includes two directions to get a precise understanding, such as the TSV filling and solder bumping, and explores their reliability aspects. TSV filling addresses the DRIE (deep reactive ion etching) process, including the coating of functional layers on the TSV wall such as an insulating layer, adhesion layer, and seed layer, and TSV filling with molten solder. Solder bumping processes such as electroplating, solder ball bumping, paste printing, and solder injection on a Cu pillar are discussed. In the reliability part for TSV and solder bumping, the fabrication defects, internal stresses, intermetallic compounds, and shear strength are reviewed. These studies aimed to achieve a robust 3D integration technology effectively for future high-density electronics packaging.

Three-Dimesnional Semicondoctor Stacking using TSV(Through-Si-Via) Technology

Recently, the electronics industry is developing toward artificial intelligence, the Internet of things, fifth-generation technology, and high-performance computing. High-density electronics packaging, high speed, high performance, and miniaturized size are required to satisfy these trends. Three-dimensional Si-chip stacking using through-Si via (TSV) has attracted the attention of industries related to these requirements. In this study, TSV fabrication using the deep reactive ion-etching process and the coating of functional layers on the TSV wall, such as insulating, adhesion, and seed layers, were investigated. In addition, Cu electroplating in the TSV was analyzed in detail. The solutions to other accompanied technical barriers for packaging high-density electronics can improve smartness and con- venience. Key words: Three dimensional packaging, Through-Si-Via, Functional layers, Electroplating

3-D CMOS Chip Stacking for Security ICs Featuring Backside Buried Metal Power Delivery Networks With Distributed Capacitance

3-D stacks of complimentary metal-oxide-semiconductor (CMOS) integrated circuit (IC) chips for security applications monolithically embed backside buried metal (BBM) routing with low series impedance and high decoupling capability in a power delivery network (PDN), thanks to distributed capacitances over a full-chip backside area. The 3-D Si demonstrator integrating cryptographic engines was fabricated in a 0.13-μm CMOS technology with post-Si wafer-level BBM Cu processing with 10, 15, and 10 μm of thickness, linewidth, and space, respectively, along with through Si vias (TSVs) with 10 and 40 μm of diameter and depth, respectively. The capacitance of 0.18 nF/mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> in the effective backside area of 71 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> suppressed dynamic IR drops in 10% and 59% for the single chip and four chip stack samples, respectively, during the operation of a 3.9 M-gate crypto core at 30 MHz. On-chip power noise monitoring (OCM) was applied in these measurements. The 3-D BBM PDN also effectively reduces power side channel information leakage, which is evaluated by 14× increase in the number of externally observed electromagnetic (EM) noise waveforms to attain the t-test value of larger than 4.5.

Co-precipitation of MnO and Cu in an ionic liquid as a first step toward self-formed barrier layers

Mixed MnO–Cu nanoparticles are synthesised in an ionic liquid, and the suspensions are spread and annealed directly on technological substrates to form films suitable for the metallisation of through-Si vias.

Experimental characterisation of coaxial TSV transistor keep out zones

Three-dimensional (3D) integration is an emerging technology that aims to achieve efficient packaging of the multifunctional silicon (Si) die within a single chip package. This system in package approach achieves connectivity between the individual Si die using through Si via (TSV) technology. Coaxial TSVs have emerged as the preferred 3D interconnect for high-frequency packaging applications due to their superior high-frequency electrical characteristics. The interconnect utilises a copper shield to prevent noise and unwanted signal coupling to occur within the Si substrate. However, a potential disadvantage of 3D integration is the large transistor keep-out-zones (KOZs) required to prevent transistor variability caused by thermally induced stress due to the copper-based TSVs in the Si substrate. Currently, only analytical models exist that predict KOZs for various coaxial TSV configurations and determining the precise KOZ is critical to minimise interconnect footprint that results in increased costs due to reductions in Si die area for integrated circuit designers. For the first time, the work has characterised the thermomechanical behaviour of fabricated coaxial TSVs utilising the microRaman spectroscopy technique to define transistor KOZ for both analogue and digital circuital applications.

Effect of Via Pitch on the Extrusion Behavior of Cu-filled TSV

In this study, the extrusion behavior of Cu fill material in a through-Si-via (TSV) subjected to thermal loading was investigated. The Cu filling of the TSV was accomplished using pulse periodic reverse (PPR) electroplating. To study the extrusion, TSVs of varying via pitch were filled with Cu by electroplating. Defect-free Cu filling of the TSV was obtained at a Cathodic Current Density (CCD) of -5 mA/cmA/cm2. The Cu-filled TSVs were subjected to annealing at 450 °C and the extrusion heights were measured. Microstructural characterizations were performed by scanning electron microscopy (SEM) and atomic force microscopy (AFM). The experimental results were also validated using finite element analysis (FEA). The results indicated that as the distance between via holes, i.e., pitch, decreased from 40 to 20 μm, the extrusion heights were found to increase. In other words, the extrusion height increases due to the mutual influence between vias when the spacing of the vias is reduced. The simulated extrusion heights of the Cu-filled TSVs were in good agreement with the experimental results. The FEA simulation results also indicated an overall increasing tendency of extrusion heights when via pitch decreased. Key words: extrusion, through-silicon-via, electroplating, finite element method, thermal expansion coefficient

Self-Anchored Catalyst Interface Enables Ordered Via Array Formation from Submicrometer to Millimeter Scale for Polycrystalline and Single-Crystalline Silicon.

Defying text definitions of wet etching, metal-assisted chemical etching (MacEtch), a solution-based, damage-free semiconductor etching method, is directional, where the metal catalyst film sinks with the semiconductor etching front, producing 3D semiconductor structures that are complementary to the metal catalyst film pattern. The same recipe that works perfectly to produce ordered array of nanostructures for single-crystalline Si (c-Si) fails completely when applied to polycrystalline Si (poly-Si) with the same doping type and level. Another long-standing challenge for MacEtch is the difficulty of uniformly etching across feature sizes larger than a few micrometers because of the nature of lateral etching. The issue of interface control between the catalyst and the semiconductor in both lateral and vertical directions over time and over distance needs to be systematically addressed. Here, we present a self-anchored catalyst (SAC) MacEtch method, where a nanoporous catalyst film is used to produce nanowires through the pinholes, which in turn physically anchor the catalyst film from detouring as it descends. The systematic vertical etch rate study as a function of porous catalyst diameter from 200 to 900 nm shows that the SAC-MacEtch not only confines the etching direction but also enhances the etch rate due to the increased liquid access path, significantly delaying the onset of the mass-transport-limited critical diameter compared to nonporous catalyst c-Si counterpart. With this enhanced mass transport approach, vias on multistacks of poly-Si/SiO2 are also formed with excellent vertical registry through the polystack, even though they are separated by SiO2 which is readily removed by HF alone with no anisotropy. In addition, 320 μm square through-Si-via (TSV) arrays in 550 μm thick c-Si are realized. The ability of SAC-MacEtch to etch through poly/oxide/poly stack as well as more than half millimeter thick silicon with excellent site specificity for a wide range of feature sizes has significant implications for 2.5D/3D photonic and electronic device applications.

Electroless Metallization of Dielectric Surfaces

Methods for catalytic activation followed by electroless metal plating have been developed for their potential use for 2.5D and 3D Through - Si Vias (TSVs) packaging applications. SiOx and TiOx nanolayers with catalytic Pd particles have been deposited that are low in thickness (< 30nm) and roughness (< 2nm). Metal (Ni or Co) has been electrolessly plated with P and W to ensure low roughness and aid in limiting inter-diffusion between the metal barrier-seed layer and electroplated copper. Electroless Co or Ni films containing over 12% P and 2% W provided an effective barrier layer. These methods could be also applied to Through - Glass Vias (TGVs) substrates.

Electroless Metallization of Dielectric Surfaces

Electroless plating is a conformal and low cost deposition method that can improve the critical parameters of 3D Through-Si Vias (TSV) interconnects. It enables conformal barrier/seed layer deposition to improve the scalability and decrease the cost of TSV interconnects by replacing PVD barrier/seed method, which has the disadvantages of higher cost and poor step coverage. Another major application of selective electroless metallization technology includes transparent metal mesh for flexible displays and touch screens to replace expensive and brittle ITO. Activation of dielectric surfaces with catalytic nanolayers. Dielectric surfaces need to be activated prior to electroless plating. SiOX-NH2-Pd and TiOX-Pd activation methods were developed and characterized to achieve control growth of self-assembled catalytic nanolayers containing Pd nanoparticles. Characterization was performed using XRR, profilometry, FTIR, ellipsometry, SIMS and HR SEM. Thickness of the assembled nanolayers was measured to be < 30 nm on glass and silicon substrates. The characterization of the properties (morphology) and composition of self-assembled silane coupling agent with catalytic monolayers containing Pd nanoparticles was performed by using XRR, Profilometer and SIMS, respectively, to achieve low surface roughness (RMS <2 nm) and high uniformity (<10%, 1 Sigma) with low trace impurities (<100 ppm) of the substrate coating. The thickness of assembled catalytic nanolayers including SiOX-NH2-Pd and TiOX-Pd was measured by using XRR, ellipsometry, profilometry and HR SEM. The thickness ranges from 2 nm to 10 nm for SiOX-NHX nanolayers and from 15 nm to 30 nm for TiOX nanolayers. The surface roughness of catalytic nanolayers was measured by using XRR and profilimetry. The thickness uniformity measured at 9 points by profilometry was < 10%, 1 Sigma for SiOX-NHX and for TiOX while the surface roughness was < 2 nm for both types of nanolayers. Composition of nanolayers and trace impurities in nanolayers were characterized by FTIR and SIMS. FTIR data showed OH and CH absoption peaks in catalytic nanolayers. Composition of nanolayers (Ti, Si, Pd, CH, NH, O) were also qualitatively characterized by SIMS with no detectable trace impurities. Electroless metal deposition on catalytic nanolayers. Electroless NiWP (NiWBP) and CoWP (CoWBP) films (down to 30 nm thick) were deposited on catalytic nanolayers with surface roughness < 1 nm and thickness uniformity <10% @ 1 Sigma. The film properties were studied by using Profilometer, EPMA, XRD, DSC and HR SEM. Crystallization temperature was achieved of over 350 C for electroless Ni(Co) alloys. The concentrations of P and W in electroless plated films were over 12% and 2%, respectively. Electroless Co(Ni)WP(B)/Cu barrier/seed layers are effective barriers against copper diffusion with low surface roughness and high adhesion to the substrate. Conformal Ni alloy (Co alloy)/Cu layers were deposited on catalytic nanolayers to form barrier/seed layers for Cu interconnects. Selective and conformal (>95% step coverage) deposition of electroless Ni(Co)alloys/Cu was obtained inside TSV (< 5 µm size and > 10:1 aspect ratio) if photosensitive TiOX-Pd catalytic nanolayers were used. 5-20 μm wide Cu (up to 2 μm thick)/Ni (up to 0.1 μm thick) patterns were deposited to form copper patterns (redistribution layers, copper mesh et al). The adhesion of electroless plated metal to dielectric surface was measured to be over 65 MPa by using pull test. Plating bath metrology. Bath metrology was developed to control the quality and replenish the plating bath for both metals (Ni, Co, W, Pd) and reducing agents (hypophosphite, DMAB) in electroless plating baths (Ni, Co) with precision/tolerance (p/t) < 0.3. Standard solutions (LCL, Target, UCL) were prepared and linear calibration curves were obtained. UV-VIS analysis of Co was performed at 530 nm while UV-VIS analysis of Ni was performed at 390 nm with dilution in DI water. To analyze Pd, PdCl2 solution was diluted in IPA. To analyze tungstate, three solutions were used including solution #1: 12% SnCl2 in HCl, solution #2: 25% KSCN in DI water, and solution #3: 1.4 mL Solution #1 + 0.1 mL Solution #2. UV-VIS Absorbance data were taken at 398.5 nm. Hypophosphite and DMAB reducing agents were analyzed by using titration.

Stacked Integration of MEMS on LSI.

Two stacked integration methods have been developed to enable advanced microsystems of microelectromechanical systems (MEMS) on large scale integration (LSI). One is a wafer level transfer of MEMS fabricated on a carrier wafer to a LSI wafer. The other is the use of electrical interconnections using through-Si vias from the structure of a MEMS wafer on a LSI wafer. The wafer level transfer methods are categorized to film transfer, device transfer connectivity last, and immediate connectivity at device transfer. Applications of these transfer methods are film bulk acoustic resonator (FBAR) on LSI, lead zirconate titanate (Pb(Zr,Ti)O3) (PZT) MEMS switch on LSI, and surface acoustic wave (SAW) resonators on LSI using respective methods. A selective transfer process was developed for multiple SAW filters on LSI. Tactile sensors and active matrix electron emitters for massive parallel electron beam lithography were developed using the through-Si vias.

Evaluation of Si liquid cooling structure with microchannel and TSV for 3D application

The development of 3D integration has caused a major technology paradigm shift to all integrated circuit (IC) devices, interconnects, and packages. Despite the benefits of 3D integration, this process faces the key challenge of thermal management, especially for high power and high density IC devices. Due to the limitations of conventional thermal solutions, liquid cooling technology has become a field of great interest for IC thermal management. In this study, an on-chip liquid cooling module with three different through Si vias (TSVs) and a fixed microchannel structure has been fabricated on an Si wafer using deep reactive ion etching and anodic bonding, followed by a grinding and dicing process. Pressure drop, coolant flow, and temperature difference before and after liquid flow were experimentally measured. TSV depth and diameter have been shown to have little effect on the change of pressure drop; however, shallower TSV depth and larger TSV diameter led to improved liquid cooling performance. The trapezoidal TSV showed slightly more effective cooling than did the scalloped TSV or the straight TSV.

Experimental assessment of on-chip liquid cooling through microchannels with de-ionized water and diluted ethylene glycol

Recent progress in Si IC devices, which results in an increase in power density and decrease in device size, poses various thermal challenges owing to high heat dissipation. Therefore, conventional cooling techniques become ineffective and produce a thermal bottleneck. In this study, an on-chip liquid cooling module with microchannels and through Si via (TSV) was fabricated, and cooling characteristics were evaluated by IR measurements. Both the microchannels and TSVs were fabricated in a Si wafer by deep reactive ion etching (DRIE) and the wafer was bonded with a glass wafer by a anodic bonding. The fabricated liquid cooling sample was evaluated using two different coolants (de-ionized water and 70 wt % diluted ethylene glycol), and the effect of coolants on cooling characteristics was investigated.

Electrodeposition of Nanotwin Cu by Pulse Current for Through-Si-Via (TSV) Process.

Recently, the through-Si-via (TSV) had been focused as an optimal solution for interconnecting the 3-dimensionaly stacked semiconductor devices. One of core processes in the TSV technology is the Cu filling process which electrochemically forms the Cu in the via with high aspect ratio. The nanotwin Cu is effective candidate for replacing the conventional electrodeposited Cu due to its ultrahigh mechanical strength and good electrical conductivity. In this work, the formation of the nanotwin Cu in the TSV by applying pulse current was systematically studied. Also, TSV filling behavior by electrodeposition with pulse current was compared with direct current. The variation of mechanical properties as well as the electrical resistivity of electrodeposited Cu by the pulse current also investigated.

Dual ICP Si Etching and Vapor Deposition Polymerization Liner for Backside Via-Last TSV Packaging Process Integration

Smart ICT (Information and Communication Technology) such as “Big Data”, “Cloud computing” and Smart Functionalities such as Stand-alone Self-activating MEMS/Sensors construct Smart Systems which enable IoT (Internet of Things), IoE (Internet of Everything) thus Smart Society. To realize above-mentioned Smart Technologies, high-density, low-power consumption, wide-bandwidth, fast-operation semiconductor devices as well as smart functional devices enabled by integrating functionalities with advanced semiconductor technologies including CMOS technologies are necessary. High-density Packaging technologies such as 3D, 2.5D packaging scheme basing on TSV (through-Si via) technology and 2.1D PCB packaging are among key technologies to satisfy the requirements from the both smart semiconductor devices and smart functional devices. "Hetero 3D stacked" technologies are gathering the most attention from now on. These technologies can make a high density packaging interconnection by using TSV on the each function devises. Heterogynous 3D Si integration has great advantages over conventional 2D devices such as high packaging density, small wire length, high-speed operation, low power consumption, and high feasibility for parallel processing. But, the radical problem about the cost of TSV fabrication is not still solved. In particular, the management of barrier metal film deposition on the smooth surface is most important technology for Cu diffuse protection [1]. On the other hand, TSV isolation liner materials with high step coverage and lower temperature deposition on the smooth surface for high frequency devices will be necessary in the future. “Scallop-free” etching process has developed for TSV fabrication [2]. In this paper, our high-density packaging technologies including scallop-free, low-temperature processed TSV solution for via-last packaging scheme and 2.1D packaging solutions on large panel build-up board by semiconductor manufacturer tools will be introduced. Especially, backside Via-last TSV process integration was proposed by “A Novel Dual ICP Plasma” Si etching and low-temperature "Vapor Deposition Polymerization (VDP)" liner (< 200 degree ) for lower-cost and low-stress hetero 3D chip stacked. “A Novel Dual ICP Plasma” is using 2 RF modes mixed ICP plasma. One is high frequency RF mode. And, another is low frequency RF mode. This plasma is able to generate high-density plasma (High etch rate), and also “Scallop-free” smooth etching. This is a kind of “Non-Bosch” process. On the other hand, this dual ICP plasma can carry out “Bosch” process at the same module. This system is very unique etching tool that can use for distinguishing between "Bosch" and "non-Bosch" to TSV cost reduction.

Capacitance characteristics of low-k low-cost CVD grown polyimide liner for high-density Cu through-Si-via in three-dimensional LSI

Minimization of the parasitic capacitance arising from Cu–through-Si-vias (TSVs) has been rigorously considered in order to enhance the performances of three-dimensional (3D) LSIs. We have systematically investigated the role of chemical vapor deposited (CVD) polyimide (PI) liner in Cu-TSVs in reducing the TSV capacitance. It is confirmed that CVD grown PI greatly helps to reduce the TSV capacitance as compared to the conventional PECVD-SiO2 liner. In addition to that the presence of very small hysteresis and a negligible flat-band voltage shift along the voltage axis confirms the suitability of PI liner as dielectric in the Cu-TSVs, if it were operated below the bias voltages of ±20 V. In over all, the large reduction in capacitance along with the conformal deposition of PI in the TSVs having less than 3 µm-width with aspect ratios greater than 10 reveals that CVD grown PI has the potential application in the future 3D-LSIs with highly scaled TSV.

Effect of local stress induced by thermal expansion of underfill in three-dimensional stacked IC

A three-dimensional stacked IC (3D IC) is a one of the promising structures for enhancing IC performances. A 3D IC consists of several materials such as a Si substrate, metal for through Si via (TSV) and microbump, organic adhesive called the underfill, and so on. These materials generate a coefficient of thermal expansion (CTE) mismatch. On the other hand, heat is generated in the Si substrate during circuit operation and in the environment outside 3D IC, for example. Both the CTE mismatch and heat generation induce local stress caused by expansion of the underfill injected around metal microbumps. In this paper, we report our investigation results of the effects of adhesive expansion on transistor performances by finite element method (FEM) simulation and measurement of transistor characteristics.