(Invited) Electrochemical Deposition for Applications in the Semiconductor Industry

Abstract

This year (2023) marks the 25th anniversary of the “Damascene copper electroplating for chip interconnections” publication by P.C. Andricacos et al [1] detailing the dual-damascene process and Cu superfilling of complex structures. And even though this was neither the only electrochemistry contribution to the semiconductor industry nor the first time to report successful plating of Cu structures, it signaled that electrochemical deposition would play prominent role in downscaling race [2]. The authors described Cu superfilling of a feature having characteristic dimensions of about 1 micron. Since then, electrochemists have focused intensely on electrolyte development, optimization of deposition parameters, and improvements in plating tools and process chambers, which went hand in hand with downscaling of features to be filled. Cu was plated on resistive substrates and alternative seeds, various surface pretreatments were applied, and nucleation and growth phenomena studied [3-6], until the focus shifted to alternative metals, such as Co [7]. While Chemical vapor deposition (CVD) and Atomic layer deposition (ALD) offer viable alternatives to electrochemical deposition (ECD) in fabrication of interconnects having width of several nanometers, new challenges and opportunities in 3D packaging and stacking appeared on the horizon. This field resembles more a ‘landscape’ than a ‘one-way street’ that damascene nano-interconnects were. While on one hand downscaling is gaining momentum here, too, there is also upscaling. For example, electrochemically deposited mega-pillars have diameters and heights exceeding hundreds of microns. More than a decade ago, a competitive race started between chemistry suppliers, tool manufacturers and scientists in the field to achieve bottom-up Cu fill of through-Si-vias (TSV) [8], structures meant to provide interconnections between vertically stacked integrated circuits. These structures had characteristic sizes an order of magnitude larger than the ones described in [1]. After demonstrating that superfilling of TSV was indeed possible, it became imperative to satisfy a plethora of production-line requirements, such as optimization of plating time or control of the so-called Cu pumping, a plastic deformation of Cu upon annealing. Plastic deformation leads to an uneven top surface and challenges in stacking layers on top of each other and is, therefore, undesirable. Today, researchers are contemplating possible benefits of the plastic deformation in Cu structures to establish a more robust and reliable Cu-to-Cu bonding process. Achieving defect-free fill of features was never the only requirement to be satisfied, but the ability to control plastic deformation in Cu features, or fabricate structures with specific texture, grain size, crystal structure [9, 10] on sub-micron scale, might require more thorough modifications of the current Cu plating processes. We will review this and other current trends in electrochemical deposition for applications in ‘classical’ semiconductor industry. We will also consider possibilities in technologies for Quantum computing, where a new spectrum of non-traditional candidate elements for plating could emerge [11, 12]. There, lessons learned from the downscaling of traditional interconnects could prove very useful.