Threshold Voltage Variation Research Articles

Hetero dielectric based dual material gate AlGaN channel MISHEMT for enhanced electrical characteristics

Herein, we report an AlGaN channel metal insulator semiconductor high electron mobility transistor (MISHEMT) in dual material gate (DMG) architecture with two different dielectrics as gate insulator for enhancing the DC performance of the device. The use of a high-k dielectric material as gate insulator below gate metal 1 and a low-k dielectric below gate metal 2 results in significant threshold voltage variation along the channel. This contributes to improved average carrier velocity which in turn results in better current drive. The proposed device exhibits a peak current of 162 mA/mm at zero gate bias, whereas, the DMG and single material gate (SMG) AlGaN channel HEMTs offer currents of 137 mA/mm and 125 mA/mm respectively. The peak transconductances are about 24.66 mS/mm, 23.68 mS/mm and 22.71 mS/mm respectively for the proposed device, DMG and SMG HEMTs. The proposed device reduces the OFF current by an order of 106 compared to that of DMG HEMT.

Physical understanding of a normally off p-GaN/AlGaN/GaN HEMT gate stack and a review of VTH measurement techniques

Abstract In this report a comprehensive review of the variations in threshold voltage (VTH) resulting from diverse VTH measurement bias conditions employed by leading manufacturers, as well as VTH extraction techniques is made. Notably, a standard deviation of 15% is observed in threshold voltage values due to variations in measurement bias conditions. This variation is attributed to the change in the lateral electic field conditions across gate and drain which occurs due to the change in bias conditions. Additionally, a simplified physical interpretation of the gate stack in p-GaN gate normally-off AlGaN/GaN on Si HEMTs is made. The formation of the two-dimensional electron gas (2DEG), the charge balance within the pGaN/AlGaN/GaN gate stack, and an analytical expression for threshold voltage are examined. Furthermore, various trapping mechanisms within the gate stack are reviewed to comprehend the dynamic conditions potentially contributing to threshold voltage instability during nominal operation.

Recovery of drain-induced threshold voltage shift by positive gate bias in GaN power HEMTs with p-GaN gate

We demonstrate that exposure to positive gate bias can favor a fast recovery of the threshold voltage variation induced by off-state stress, in p-GaN gate high electron mobility transistors. Two process splits were investigated, having different Schottky barriers at the metal/p-GaN junction. Results indicate that: (a) drain stress may result in significant threshold voltage increase; (b) devices with sufficiently high gate leakage current show an immediate recovery after gate turn-on, resulting in stable operation in actual applications. The contribution of leakage current is demonstrated, based on recovery experiments at different voltages and for the same rate of hole injection from the gate.

200 mm Wafer Level Characterization at 2 K of Si/SiGe Field-Effect Transistors

Si/SiGe has proven to be an excellent spin qubit platform, but industrial production of large-scale spin-qubit chips is missing. We use field effect transistors (FETs) to monitor and develop the quality of the fabrication process on 200 mm wafers at 2 K using a cryogenic wafer prober (CWP). This mass-characterization technique provides statistics on device performance. We observe variations in drain off current and gate threshold voltage of 213 FETs. These variations are related to bias voltage conditions during CWP cooldown, which differ from qubit chip cooldown. To address this, a new FET structure with an additional top gate is introduced, effectively suppressing unintentional charge accumulations. This eliminates drain off currents and improves homogeneity of FET characteristics at 2 K. Our results highlight significant impact of bias conditions during qubit chip cooldown, which, if not accounted for in the qubit chip design, can lead to incorrect conclusions when using CWP.

Polarization Pruning: Reliability Enhancement of Hafnia-Based Ferroelectric Devices for Memory and Neuromorphic Computing.

Ferroelectric (FE) materials are key to advancing electronic devices owing to their non-volatile properties, rapid state-switching abilities, and low-energy consumption. FE-based devices are used in logic circuits, memory-storage devices, sensors, and in-memory computing. However, the primary challenge in advancing the practical applications of FE-based memory is its reliability. To address this problem, a novel polarization pruning (PP) method is proposed. The PP is designed to eliminate weakly polarized domains by applying an opposite-sign pulse immediately after a program or erase operation. Significant improvements in the reliability of ferroelectric devices are achieved by reducing the depolarization caused by weakly polarized domains and mitigating the fluctuations in the ferroelectric dipole. These enhancements include a 25% improvement in retention, a 50% reduction in read noise, a 45% decrease in threshold voltage variation, and a 72% improvement in linearity. The proposed PP method significantly improves the memory storage efficiency and performance of neuromorphic systems.

Suppression of Threshold Voltage Variation by H₂ Plasma Improved KrF Photoresist Profile

Suppression of Threshold Voltage Variation by H₂ Plasma Improved KrF Photoresist Profile

Impacts of quantum confinement effect on threshold voltage and drain-induced barrier lowering effect of junctionless surrounding-gate nanosheet NMOSFET including source/drain depletion regions

In order to modeling of junctionless (JL) surrounding-gate (SG) nanosheet MOSFET more accurately, a new model for determining threshold voltage and drain-induced barrier lowering (DIBL) effect of JL SG nanosheet NMOSFET is proposed through deriving the Poisson's equation under rectangular coordinate system. The model captures quantum confinement effect and source/drain depletion regions, it is validated through the Sentaurus TCAD simulation results. Variations of source/drain depletion regions with the channel width, height, doping concentration, the gate bias, the drain bias and variations of threshold voltage, DIBL with the channel width, height, doping concentration considering and not considering quantum confinement effect are studied, respectively. The results show influences of quantum confinement effect on source/drain depletion regions, threshold voltage and DIBL. The developed model will offer quantum corrections in JL SG nanosheet NMOSFET.

Subthreshold read operations in 3D PCM: 1S1R device modeling and memory array analysis

3-D phase change memory (PCM) is one of the most promising next-generation nonvolatile memory, and the subthreshold sensing strategy can effectively improve its limited endurance. In this study, we propose a one-selector-one-resistor (1S1R) model with Monte Carlo (MC) function and provide array configurations for the worst case and the maximum bit line voltage (VBL-max), respectively. Based on these, the read window margin (RWM) is evaluated with various array sizes, OTS threshold voltage variations (σvar), and bias voltages (VBias). Our results reveal that the RWM increases as the VBL approaches the VBL-max. Larger arrays lead to an increased leakage current difference, while larger σvar values result in decreased cell current difference and VBL-max. The decrease in VBL-max further deteriorates the RWM. Additionally, we analyze the optimal VBias for 2-deck arrays achieves a 7% reduction in leakage energy consumption and a 22.6% increase in RWM compared to the V/2 bias. The optimal VBias depends on OTS devices and array sizes.

50‐3: Invited Paper: An Active‐Matrix High‐Channel‐Count Neurostimulation System Enabled by Flexible Thin‐Film Transistors

Advanced neurostimulation systems require intimate interface with brain or peripheral nervous system to provide a therapeutic modulation for patients experiencing neural function loss. To achieve these, it requires stimulators with high‐channel counts and mechanical flexibility. In this invited paper, we showed a 4T1C neurostimulation pixel circuit with an active‐matrix architecture, offering the opportunity for high‐channel counts. In addition, a 4‐mask photolithographic process for highly uniform organic thin‐film transistor (OTFT) integrated system was demonstrated for mechanical flexibility, which shows a high device yield of 100% (50/50) and small device variation in threshold voltage of 0.64 V and in mobility of 4.9%. By implementing OTFTs to this novel neurostimulation architecture, we fabricated an OTFT‐based high‐channel‐count neurostimulation system, showing a high stimulator yield of 71.0% and small variation of 15.6% for the output stimulation currents among pixels.

10‐4: Late‐News Paper: Precise Compensation of Device Variability in IGZO‐based Ferroelectric Thin‐Film Transistors for Enhanced Transparent Display Performance

We demonstrate the compensation of device‐to‐device variation in threshold voltage using programmable ferroelectric indium‐gallium‐zinc‐oxide thin‐film transistors. Furthermore, degradationinduced threshold voltage shift can be mitigated by programming, setting the characteristics back to their pristine state. This can be a promising alternative for the replacement of complex VT compensation circuits in display applications.

P‐68: Oxide Semiconductor Thin‐Film Transistor‐Based Micro‐LED Pixel Circuit with External Current Setting System

We propose an oxide semiconductor thin‐film transistor‐based micro light‐emitting diode pixel circuit with external current setting system. The proposed circuit achieved stable operation using pulse width modulation with maximum error rates 1.2 % and 3.2 % under threshold voltage variations and mobility variations, respectively.

71‐3: High Resolution Pixel Circuit Using a Double‐Gate LTPS TFT for AMOLED Displays in AR and VR Applications

The new AMOLED pixel circuit for high‐resolution applications such as AR/VR has been proposed. The simultaneous emission is adopted to minimize pixel elements. The proposed circuit can compensate for variations of threshold voltage and sub‐threshold voltage even composed with 3 TFTs and 1 capacitor.

P‐72: A Bidirectional Gate Driver Circuit with Scan Signal for Low‐Frame‐Rate LTPO AMOLED Displays

This paper presents a bidirectional gate driver circuit based on low‐temperature polycrystalline oxide thin‐film transistors for a low‐frame‐rate AMOLED display. Simulation results indicate the falling and rising times of the output waveform are all below 3.48 μs and 0.56 μs with the threshold voltage variations of TFTs, ensuring the stability of the proposed circuit. The output waveforms are also generated successfully for a frame rate of 1 Hz display panel and have no fluctuation in consecutive frames. Therefore, the proposed circuit is suitable for a low‐frame‐rate AMOLED display.

79‐3: Novel Mini‐LED Pixel Circuit with PWM Driving Method for Decreasing Power Consumption

This article proposes a mini‐LED pixel circuit that employs the PWM driving method to decrease power consumption. To achieve uniform current, the circuit compensates for threshold voltage variations of TFTs and VDD I‐R drops. Simulation results show that power consumption is ameliorated over 10.53% more than the 6T1C circuit.

High Mobility Amorphous Polymer‐Based 3D Stacked Pseudo Logic Circuits through Precision Printing

AbstractDirect printing of conjugated polymer thin‐film transistors enables the fabrication of deformable devices with low cost, high throughput, and large area. However, a relatively poor device performance of printed devices remains a major obstacle to their application in high‐end display backplanes and integrated circuits. In this study, high‐performance and highly stackable printed organic transistors is developed, arrays, and circuits using a near‐amorphous polymer, indacenodithiophene‐co‐benzothiadiazole (IDT‐BT). The printed devices exhibited high saturation mobility (>1 cm2 V−1 s−1), high on/off ratio (>107), and low subthreshold slope (245 mV dec−1). In addition, 16 × 16 printed IDT‐BT arrays achieved 100% fabrication yield, with excellent device‐to‐device uniformity and low variations of mobility (9.55%) and threshold voltage (4.51%), and good operational and environmental stability (>365 days). Furthermore, five stacked 3D transistors are demonstrated with an excellent 3D uniformity without compromising device performance due to a low required thermal budget for processing amorphous IDT‐BT. Finally, a new concept of 3D universal logic gate with high voltage gain (33.91 V/V) and record density (100 printed transistors per cm2) is proposed and fabricated, which is relevant for the commercialization of low‐cost printed display backplanes and high‐density integrated circuits based on highly processable polymeric semiconductors.

An energy-efficient design of ternary SRAM using GNRFETs

ABSTRACT The primary requirement of internet-of-things (IoT) applications is to have an energy-efficient design that extends the battery life for long-term operation. To achieve energy efficiency, one can employ multiple-valued logic (MVL) instead of binary logic and utilise graphene nanoribbon field-effect transistors (GNRFETs) as variable-threshold voltage (V th ) capable devices. The implementation of an MVL system enhances data transferability and reduces the number of interconnections, resulting in improved energy consumption compared to a binary system. In such systems, static random access memory (SRAM), which serves as a crucial component of very large-scale integrated (VLSI) chips, dominates energy consumption. This research paper introduces an energy-efficient ternary SRAM using GNRFETs. We propose a standard ternary inverter based on GNRFET devices, which serves as the fundamental building block of a storage cell. Simulation results conducted on a 32-nm GNRFET with a 0.9 V supply voltage demonstrate that the proposed design achieves energy consumption improvements ranging from 46.39% to 98.16% compared to the most recent ternary SRAMs. Furthermore, the SRAM cell is evaluated under various processes and environmental parameter variations.

Threshold voltage uniformity improvement by introducing charge injection tuning for low-temperature poly-Si thin film transistors with metal/oxide/nitride/oxide/silicon structure

Low-temperature poly-Si thin film transistors (TFTs) with a metal/oxide/nitride/oxide/silicon structure were fabricated to investigate the feasibility of suppressing threshold voltage variations between TFTs. By applying relatively high positive and negative gate bias voltages, threshold voltage could be tuned positively and negatively, respectively, by injecting charges into the charge trap layer. Stability of threshold voltage against positive gate bias at a level close to the actual circuit operation was not degraded compared with the case of an as-fabricated TFT. A uniform threshold voltage distribution could be achieved in a preliminary test using 16 TFTs by converging threshold voltages with a target value by tuning the threshold voltage for each TFT.

Voltage-time dilemma and stochastic threshold-voltage variation in pure-silver atomic switches

Voltage-time dilemma and stochastic threshold-voltage variation in pure-silver atomic switches

A 6T1C pixel circuit compensating for TFT electrical characteristics variations, voltage drop, and OLED degradation

A voltage-programmed pixel circuit based on low-temperature poly-silicon (LTPS) thin-film transistors (TFTs) is presented for active-matrix organic light-emitting diode (AMOLED) displays. The circuit consists of six p-type transistors and one capacitor (6T1C). During the extraction stage, the circuit extracts the driving TFT’s threshold voltage and the power supply voltage. During the data input stage, the circuit generates a charging voltage, which is associated with the driving TFT’s mobility and the OLED’s threshold voltage. Consequently, the pixel circuit, using only one capacitor, compensates not only for the TFT’s electrical characteristics variations, i.e., the threshold voltage variation and mobility variation, but also for the power supply voltage drop and the OLED degradation. The circuit simulation results reveal that the OLED current error rates (CERs) are lower than 5.09% when the threshold voltage varies by ±0.5V, lower than 3.61% when the mobility varies by ±30%, and lower than 9.16% when the voltage drop varies by −0.5V in the data voltage range.

Reliability of enhancement-mode p-GaN gate GaN HEMT with multiple field plates

In this paper, we fabricate enhancement-mode p-GaN gate GaN HEMTs with multiple field plates (MFPs) and analyze the reliability of the devices by means of simulation and experiment. Simulations of the electric-field distribution indicate that the MFPs effectively weaken the electric field peak near the gate to below the theoretical breakdown value and smooth the electric field between the gate edge and drain-side field plate edge. The simulated electric field peak leading to the breakdown of the device with MFPs at high drain voltage is located at the drain edge, which is validated by experimental results. The GaN HEMTs with MFPs exhibit excellent long-term reliability under high temperature and drain voltage, while deviations from threshold voltage and on-resistance were observed in the device subjected to drain stress. We attribute these deviations to electron accumulation and high field-assisted detrapping processes in the p-GaN layer. This investigation provides new insight into the mechanism of variations in threshold voltage and on-resistance under off-state drain stress.