Threshold Voltage Drift Research Articles

Study of the Bias Driven Threshold Voltage Drift of 1.2 kV SiC MOSFETs in Power Cycling and High Temperature Gate Bias Tests

Threshold voltage instability remains a challenging aspect for metal-oxide semiconductor-field-effect-transistors (MOSFETs) made from silicon carbide (SiC). SiC MOSFETs from two manufacturers, with planar and trench gate structure respectively, have been tested under different test procedures, including power cycling and high temperature gate bias tests. The standard power cycling test setup has been modified to enable an in situ threshold voltage read-out procedure with the hysteresis method. The recorded threshold voltage drift has been compared with results from high temperature gate bias tests applying a simple power law fit, with the intention to predict the drift in power cycling tests. For the group with trench MOSFETs comparable results between power cycling and gate stress tests have been achieved.

Dynamic Bias-Temperature Instability Testing in SiC MOSFETs

For power converter development in mission critical applications, the attractive performances of SiC power MOSFETs are shadowed by reliability concerns, particularly those induced by the defects at the gate dielectric. Charge trapping at the oxide-semiconductor interface can lead to threshold voltage drift, degrading the power converter efficiency and lifetime. The scope of this contribution is to show a testing methodology under development to understand SiC power MOSFET threshold voltage stability under dynamic and accelerated operating conditions. The presented testing methodology relies on switching the device under test at high-voltage and current, simultaneously applying a gate stress and extracting threshold voltage from switching transients. The paper outlines the setup description, its operating modes and intended design of experiment to assess SiC MOSFET threshold voltage stability.

Thin-Film Transistor Digital Microfluidics Circuit Design with Capacitance-Based Droplet Sensing.

With the continuous expansion of pixel arrays in digital microfluidics (DMF) chips, precise droplet control has emerged as a critical issue requiring detailed consideration. This paper proposes a novel capacitance-based droplet sensing system for thin-film transistor DMF. The proposed circuit features a distinctive inner and outer dual-pixel electrode structure, integrating droplet driving and sensing functionalities. Discharge occurs exclusively at the inner electrode during droplet sensing, effectively addressing droplet perturbation in existing sensing circuits. The circuit employs a novel fan-shaped structure of thin-film transistors. Simulation results show that it can provide a 48 V pixel voltage and demonstrate a sensing voltage difference of over 10 V between deionized water and silicone oil, illustrating its proficiency in droplet driving and accurate sensing. The stability of threshold voltage drift and temperature was also verified for the circuit. The design is tailored for integration into active matrix electrowetting-on-dielectric (AM-EWOD) chips, offering a novel approach to achieve precise closed-loop control of droplets.

Design optimization of wide-gate swing E-mode GaN HEMTs with junction barrier Schottky gate

To increase the gate swing, a GaN-based high-electron-mobility transistor with a junction barrier Schottky gate (JBS-HEMT) was proposed. Compared to conventional p-GaN Schottky gate HEMTs (Conv-HEMT), the high electric field at the surface is transferred to the pn junction inside the body, and the extended depletion region of the pn junction shields the surface Schottky contact interface for the JBS-HEMT. After fitting the model to the reported device, the proposed JBS-HEMT was simulated and optimized using the Sentaurus TCAD tool. The simulation results of the optimized JBS-HEMT demonstrate a high gate breakdown voltage (17.6 V), which is 158.5% higher than the gate breakdown voltage of the Conv-HEMT (11.1 V) and a lower gate leakage current of six orders of magnitude than the Conv-HEMT at the gate-to-source voltage of 10 V. The proposed JBS-HEMT exhibits a positive threshold voltage (1.68 V) and excellent threshold voltage stability, and the maximum threshold voltage drift of the JBS-HEMT (+0.237 V) is smaller than that of the Conv-HEMT (−0.714 V) under gate stress conditions. The peak transconductance of the JBS-HEMT (186 mS mm−1) at athe drain-to-source voltage of 10 V showed almost no reduction compared to the Conv-HEMT (189 mS mm−1), which solves the problem of decreased transconductance capability of the reported GaN HEMT with a p-n junction gate (PNJ-HEMT). It was confirmed that the JBS-HEMT has excellent gate stability and potential for power electronics applications.

Adjustable Super‐linear Photoresponse via Organic Phototransistors with Graded Active Layer Toward Intelligent Contrast Control

AbstractGenerally, photocurrent achieves saturation easily under high light intensity and/or high current density by exciton/carrier quenching; to the best of authors knowledge super‐linear photoresponse has not been observed experimentally in all types of photodetectors before. This study has reported super‐linear photoresponse organic phototransistors (OPTs) based on bulk heterojunction (BHJ) with PM6 as the donor and Y6 as the non‐fullerene acceptor. The super‐linear photoresponse has satisfied that the photocurrent is proportional to the 1.37 power of light intensity (linearity index ∂ = 1.37), in which gain achieves 280% (external quantum efficiency, EQE greater than 1) and detectivity (Dshot*) achieves 1.88 × 1013 Jones at Vg of 5 V. The quick minority carrier release of non‐fullerene acceptor can help reduce the threshold voltage drift and match the transconductance, improving the possibility of obtaining super‐linear response regions. The graded distribution of donor/acceptor is more likely to reduce carrier quenching under high light intensity during the extension of Debye screening layer for effective super‐linear response. By modulating the gate voltage, the linearity index can be adjusted from 0.5 to 2.33, where the super‐linear photoresponse can automatically enlarge the contrast of the image. It has an excellent application prospect in intelligent contrast control in real time image recognition.

Research on the Reliability of Threshold Voltage Based on GaN High-Electron-Mobility Transistors.

With the development of high-voltage and high-frequency switching circuits, GaN high-electron-mobility transistor (HEMT) devices with high bandwidth, high electron mobility, and high breakdown voltage have become an important research topic in this field. It has been found that GaN HEMT devices have a drift in threshold voltage under the conditions of temperature and gate stress changes. Under high-temperature conditions, the difference in gate contact also causes the threshold voltage to shift. The variation in the threshold voltage affects the stability of the device as well as the overall circuit performance. Therefore, in this paper, a review of previous work is presented. Temperature variation, gate stress variation, and gate contact variation are investigated to analyze the physical mechanisms that generate the threshold voltage (VTH) drift phenomenon in GaN HEMT devices. Finally, improvement methods suitable for GaN HEMT devices under high-temperature and high-voltage conditions are summarized.

Study of the Influence of Different Gate Oxide Traps on Threshold Voltage Drift of SiC MOSFET based on Transient Current

Study of the Influence of Different Gate Oxide Traps on Threshold Voltage Drift of SiC MOSFET based on Transient Current

Improving the selector characteristics of ovonic threshold switch via UV treatment process

In this study, we investigated the influence of ultraviolet (UV) treatment on the ovonic threshold switch (OTS) to improve its selector properties. Our findings demonstrate that iteratively applying UV treatment during the film deposition phase considerably improves device characteristics compared to a single UV treatment. Consequently, this process provided a significant decrease in the forming voltage, maintaining outstanding switching features, with an off-state current of approximately 2 nA. Furthermore, the refined UV treatment process resulted in an impressive 45% improvement in threshold voltage drift characteristics and facilitated excellent switching uniformity. X-ray photoelectron spectroscopy analysis revealed alterations in the bonding structure of the Si–Te–As–Ge film after UV exposure. Specifically, a transition was observed from unstable homopolar bonds, such as As-As or Te–Te, to their more stable heteropolar equivalents, such as As–Te. These results highlight the potential of UV treatment as an effective method for enhancing the OTS performance.

Excellent Reliability Characteristics of Ovonic Threshold Switch Device with Higher‐Temperature Forming Technique

Amorphous chalcogenide‐based ovonic threshold switch (OTS) has significant potential as a selector device in high‐density memory arrays. However, to realize the ideal selector device, OTS still needs to enhance its reliability characteristics such as device uniformity and threshold voltage (Vth) drift. Herein, the effect of elevated temperature forming on the selector characteristics of an OTS device is investigated. The findings indicate that the reliability performance of the device significantly improves when the forming process is conducted at higher temperature. In particular, it shows excellent Vth uniformity (σ = 32 mV) and a notable enhancement in the Vth drift characteristics. Based on trap analysis at cryogenic temperature (77 K), it is confirmed that improved reliability characteristics can be attributed to the stability of the activated trap formed by the HT forming process.

Numerical Simulation of Hetero Dielectric Trench Gate JAM Gate-All-Around FET (HDTG-JAM-GAAFET) for Label Free Biosensing Applications

The label free detection of various biomolecules associated with different diseases has been proposed in this manuscript using a novel biosensor design named as the Hetero Dielectric Trench Gate Junctionless Accumulation Mode Gate-All-Around FET (HDTG-JAM-GAAFET). This biosensor employs a silicon cylindrical Gate All Around FET which operates in Junctionless Accumulation Mode (JAM) and has a hetero dielectric layer comprised of SiO2 and HfO2. The cylindrical gate structure’s metal gate is trenched into the Hafnium oxide dielectric layer, which provides the gate with enhanced control over the surface characteristics of the channel. A Trench Gate architecture in a hetero dielectric Gate All Around FET is emulated for the biosensing for the first time. The HDTG-JAM-GAAFET has been compared to Normal Gate JAM Gate-All-Around FET (NG-JAM-GAAFET) biosensors immobilizing a variety of neutral biomolecules and biomolecules having a range of positive and negative charges. The effect of biomolecules on HDTG-JAM-GAAFET biosensor’s output properties, including surface potential, electron concentration, threshold voltage drift (ΔVTH), subthreshold leakage current (IOFF), subthreshold slope (SS), switching ratio (ION/IOFF), ION current sensitivity, transconductance (gm), output conductance (gd), channel resistance (Rch) and intrinsic gain ( AVint ) has been studied. For instance, HDTG-JAM-GAAFET biosensor has drain ON-current sensitivity (SION) which is 67.68% greater for gelatin biomolecules, 69.4% higher for positive biomolecules, and 8% higher for negative biomolecules bound in the nanogap cavity than that of a Normal Gate JAM Gate-All-Around FET. The proposed device exhibits exceptional performance characteristics and it can effectively identify specific biomolecules to diagnose many diseases, such as breast cancer, lung cancer, and numerous viral infections, using their respective biomarkers.

Reliable Gate Driving of SiC MOSFETs With Crosstalk Voltage Elimination and Two-Step Short-Circuit Protection

The over-stress of the negative gate-source voltage of SiC MOSFET, even in a short period of time, could cause the threshold voltage drift of the device, resulting in increased on-state resistance. In this paper, we propose an integrated gate driver to specially limit the peak negative gate voltage of SiC MOSFETs introduced by the crosstalk phenomenon and the reliable short-circuit protection. A simple auxiliary branch with bidirectional blocking capability is adopted in crosstalk voltage suppression and the negative peak voltage of the gate, introduced by common source inductor, is eliminated by the high impedance gate driving loop. Furthermore, the auxiliary circuit is re-used to assist a two-step short-circuit protection of the device by identifying dc-link shoot-through current on the stray inductor. By rapidly reducing the gate-source voltage to a lower value when short-circuit happens, the short circuit withstanding time of the device is prolonged, enabling a longer allowable detection time to confirm the fault event accurately. The proposed method comprehensively integrates the crosstalk voltage suppression and short circuit protection together and is verified by the experiments.

Role of interface/border traps on the threshold voltage instability of SiC power transistors

In this paper the role of interface/border defects on the threshold voltage drift (ΔVTH) of SiC power MOSFETs has been investigated by means of slow and fast positive bias temperature instability (PBTI), hysteresis and conductance tests. Results have shown an opposite temperature (T) dependency based on the level of the applied gate bias (VG) and on the adopted stress technique. With VG > 30 V and a slow-PBTI procedure, the creation of new oxide defects and/or the charge trapping in deep states occurs, showing a positive T-dependency. On the contrary, with a lower VG and a fast-PBTI test, the ΔVTH shows a negative T-dependency, associated to dominant role of pre-existing interface and/or border traps.

Impact of Bias Temperature Instabilities on the Performance of Power Electronics Employing SiC MOSFETs

In this work a reliability study of SiC power MOSFETs working as switching elements in a DC-DC Boost converter circuit is discussed. A critical parameter for a high-performance operation is the stable characteristics of the transistors employed. However, charge trapping effects such as bias temperature instabilities can affect e.g. the threshold voltage of transistors and thus lead to a variation in circuit behavior and efficiency. Furthermore, a time-dependent drift of the threshold voltage (ΔVth) of the MOSFET over time can cause an increase of the on-resistance (RDS(ON)) too, and thus affect the static on-state power losses accordingly (PON). In this work, we use our physical reliability simulator Comphy to extract the threshold voltage drift of the transistor over time for various mission profiles for gate biases under device operation. Using the extracted ΔVth values from the simulator, we can reproduce the measured behavior of the DC-DC boost converter circuit. With the calibrated toolset, we can obtain the ΔVth values over a long operation time to predict the aged behavior of the circuit parameters employing Spice simulations, which could be beneficial for circuit design and lifetime prediction of the system.

Improving the GeAsSe Ovonic Threshold Switching Characteristics by Carbon Buffer Layers for Ultralow Leakage Current (∼0.4 nA) and Low Drift Characteristics

Volatile Ovonic threshold switching (OTS) selectors have been regarded as the critical component of highly integrated three-dimensional (3D) cross-point array nonvolatile memory systems. However, relatively high leakage current hinders the further reduction of power consumption in the crossbar array. In addition, the threshold voltage drift phenomenon hinders the improvement of device reliability. Utilizing the buffer layer can effectively reduce the interaction between electrodes and the active layer in the cross-point architecture. Here, it manifests that leakage current can be reduced to ∼0.4 nA with a 5 nm thick amorphous carbon layer as a buffer layer in the GeAsSe-based OTS device, where the carbon layer stabilizes the composition of GeAsSe during the electrical switching cycles. It is also found that the carbon layer leads to a lower threshold voltage drift (35.6 mv/dec) and excellent endurance (>109 cycles with ∼0.4 nA ON-state current). The conduction mechanism analysis demonstrates that the inhibition of the carbon layer on drift originates from the high barrier height from delocalized states transformed into localized states. This work clearly demonstrates the role of the carbon layer and facilitates future 3D crossbar-storage technology applications.

Hypothesis to Explain Threshold Drift due to Dynamic Bipolar Gate Stress

We supply a hypothesis that explains threshold voltage (Vth) drift under dynamic bipolar gate stress in SiC-MOSFETs, postulating that ionized donor-like interface traps in the lower half of the bandgap, give rise to an increased internal electric field at each rising edge of a gate voltage pulse. The enhancement of the internal electric field may be viewed as a Vth -reduction, and we devised different experiments to assess this Vth -reduction. Comparing Vth -drift rate using different pulse shapes in dynamic bipolar gate stress tests, we estimated a temporary Vth -reduction in the order of 15 V within 200 ns after the rising edge. Measuring the drain-source current peak 200 ns after the rising edge of a rectangular pulse, gives an estimate for the Vth -reduction of 5.5 V. To resolve this discrepancy, we postulate that in inversion, positive traps are effectively screened such that the impact on the channel is spatially restricted and smaller than the channel length. Channel current will only flow where positive charges induce a percolation path between drain and source, reducing the apparent Vth -reduction in the current based measurement.

Remaining Useful Lifetime Prediction Based on Extended Kalman Particle Filter for Power SiC MOSFETs.

Nowadays, the performance of silicon-based devices is almost approaching the physical limit of their materials, which have difficulty meeting the needs of modern high-power applications. The SiC MOSFET, as one of the important third-generation wide bandgap power semiconductor devices, has received extensive attention. However, numerous specific reliability issues exist for SiC MOSFETs, such as bias temperature instability, threshold voltage drift, and reduced short-circuit robustness. The remaining useful life (RUL) prediction of SiC MOSFETs has become the focus of device reliability research. In this paper, a RUL estimation method using the Extended Kalman Particle Filter (EPF) based on an on-state voltage degradation model for SiC MOSFETs is proposed. A new power cycling test platform is designed to monitor the on-state voltage of SiC MOSFETs used as the failure precursor. The experimental results show that the RUL prediction error decreases from 20.5% of the traditional Particle Filter algorithm (PF) algorithm to 11.5% of EPF with 40% data input. The life prediction accuracy is therefore improved by about 10%.

Total-ionizing dose irradiation induced degradation behavior and mechanism of the Cascode GaN HEMTs

In this article, the effects of total ionizing dose (TID) irradiation and the annealing treatment on the degradation of the commercial Cascode GaN high-electron-mobility transistors (HEMTs) were investigated, and low frequency noise method (LFN) was carried out to analyze the defects. The DC characteristics show that the device after TID irradiation with different doses exhibits a negative drift of threshold voltage (V th) and a remarkable increase of drain-source current (I ds) with respect to the fresh one. Meanwhile, with increasing doses of the TID irradiation, the off-state drain leakage current increases, while the drain-source resistance decreases. The gate-lag characteristic gets better for the Cascode GaN HEMTs after TID irradiation. The transfer characteristics, output characteristics, blocking characteristics and capacitance characteristics of the devices can partly be restored by annealing treatment, but there is no pronounced influence on the gate-lag characteristics and drain-source resistance. The trap density extracted by the LFN method decreases in the Cascode GaN HEMTs after TID irradiation. The degradation behavior and mechanism of the Cascode GaN HEMTs under TID irradiation are analyzed. The experimental results may provide a useful reference for the design and space application of the Cascode GaN HEMTs.

Amorphous Ge-Se-S chalcogenide alloys via post plasma sulfurization of atomic layer deposition GeSe for ovonic threshold switch applications

For the future scaling of 3D cross-point (X-point) memory, it is necessary to implement atomic layer deposition (ALD) of chalcogenides for ovonic threshold switch (OTS) applications. We investigated ternary Ge-Se-S amorphous chalcogenide alloys based on ALD process, motivated by the expectation of low off-current and stable OTS behavior by partially replacing S in binary Ge-Se. Ge-Se-S alloys were synthesized by post-deposition sulfurization of ALD GeSe2 thin films. Especially, we investigated the growth characteristics and film properties of ALD GeSe2 using HGeCl3 precursors with Se(SiMe3)2 together with density-functional theory (DFT) calculations. By changing the temperature and the low-temperature plasma sulfurization time, the compositions of 10-nm-thick Ge-Se-S thin films were controlled along the GeSe2-Ge2S pseudo-binary line in ternary phase diagram. It was confirmed that the Ge5Se3S2 alloys maintained an amorphous phase and excellent step coverage, similar to ALD GeSe2. Finally, we compared the OTS electrical characteristics of 10-nm-thick ALD GeSe2 with Ge5Se3S2 amorphous chalcogenide thin films in a mushroom-type device with a 50-nm bottom electrode. The novel Ge5Se3S2 had a slightly larger threshold voltage (Vth) drift than GeSe2 but exhibited the advantages of a higher threshold field, lower off-current, and smaller Vth fluctuation up to 106 cycles. Data availabilityThe data that has been used is confidential.

Total ionizing dose radiation hardening technology based on double-charge multiple-step ion implantation

This paper describes the total ionizing dose (TID) radiation hardening of buried oxide in separation by implantation of oxygen silicon on insulator (SOI) substrates. In this study, 0.5-μm partially depleted SOI complementary metal–oxide–semiconductor (CMOS) transistors and circuits were prepared using double-charge multiple-step ion implantation and annealing, and the changes in the drive current, leakage current, and threshold voltage of the CMOS transistor under different TID radiation conditions were compared. Under a TID of 500 k Rad(Si), radiation-hardened H-type N-channel metal–oxide–semiconductor transistors had a threshold voltage drift of <100 mV in the worst case, and H-type P-channel metal–oxide–semiconductor transistors had a threshold voltage drift of <150 mV. Under a TID of 1 Mrad(Si), CMOS transistors showed no significant increase in leakage current caused by TID radiation. Under a TID of 500 k Rad(Si), the standby current of the radiation-hardened 32-bit DSP was <1.5 mA. The high-density integrated circuits prepared using this technology performed well under harsh ionizing radiation environments. Finally, this technology was compared with similar foreign technologies and TID-unhardened wafers with hardened wafers. This technology reached the international advanced level among equivalent technologies regarding hole capture cross section and maximum threshold voltage drift in the model. PACS85.30.De 85.30.-e.

Working principle and characteristic analysis of SiC MOSFET

Power semiconductor devices are frequently used in the electronic and power industries. As the third-generation broadband gap power semiconductor devices, silicon carbide devices have attracted extensive attention. This paper introduces the internal and external structure of SiC MOSFET in detail and analyzes the basic working principle of SiC MOSFET and the electrical characteristics of each stage in the conductive process. By analyzing the theoretical calculation method of threshold voltage under body effect and the relationship diagram drawn by specific experimental test results, it is proved that the increase of body effect will lead to the decrease of the threshold voltage. Two main reasons for BTI characteristics are explained: the energy band shift of the SiC/SiO2 interface is small, and there are many charge traps at SiC/SiO2 interface. Finally, the theoretical calculation method of threshold voltage and the influence principle of threshold voltage drift caused by SiC/SiO2 interface charge: interface trap Qit, oxide trap Qot, movable ion Qm and fixed charge Qf are analyzed. The research on the basic principle and important characteristics of SiC MOSFET in this paper have important reference significance for improving the reliability of SiC MOSFET devices.