Role of interface/border traps on the threshold voltage instability of SiC power transistors

Abstract

In this paper the role of interface/border defects on the threshold voltage drift (ΔVTH) of SiC power MOSFETs has been investigated by means of slow and fast positive bias temperature instability (PBTI), hysteresis and conductance tests. Results have shown an opposite temperature (T) dependency based on the level of the applied gate bias (VG) and on the adopted stress technique. With VG > 30 V and a slow-PBTI procedure, the creation of new oxide defects and/or the charge trapping in deep states occurs, showing a positive T-dependency. On the contrary, with a lower VG and a fast-PBTI test, the ΔVTH shows a negative T-dependency, associated to dominant role of pre-existing interface and/or border traps.