Threshold Logic Gates Research Articles

Function synthesis algorithm based on RTD-based three-variable universal logic gates

Compared with complementary metal–oxide semiconductor (CMOS), the resonant tunneling device (RTD) has better performances; it is the most promising candidate for next-generation integrated circuit devices. The universal logic gate is an important unit circuit because of its powerful logic function, but there are few function synthesis algorithms that can implement an n-variable logical function by RTD-based universal logic gates. In this paper, we propose a new concept, i.e., the truth value matrix. With it a novel disjunctive decomposition algorithm can be used to decompose an arbitrary n-variable logical function into three-variable subset functions. On this basis, a novel function synthesis algorithm is proposed, which can implement arbitrary n-variable logical functions by RTD-based universal threshold logic gates (UTLGs), RTD-based three-variable XOR gates (XOR3s), and RTD-based three-variable universal logic gate (ULG3s). When this proposed function synthesis algorithm is used to implement an n-variable logical function, if the function is a directly disjunctive decomposition one, the circuit structure will be very simple, and if the function is a non-directly disjunctive decomposition one, the circuit structure will be simpler than when using only UTLGs or ULG3s. The proposed function synthesis algorithm is straightforward to program, and with this algorithm it is convenient to implement an arbitrary n-variable logical function by RTD-based universal logic gates.

Energy Efficient Reconfigurable Threshold Logic Circuit with Spintronic Devices

A Threshold Logic Gate (TLG) performs weighted summation of multiple binary inputs and compares the summation with a threshold. Different logic functions can be implemented by reconfiguring the weights and threshold of the same TLG circuit. This paper introduces a novel design of reconfigurable Spintronic Threshold Logic Gate (STLG), which employs spintronic weight devices to perform current-mode weighted summation of binary inputs, whereas, the low voltage fast switching spintronic threshold device carries out the threshold operation in an energy efficient manner. The proposed STLG operates at a small terminal voltage of 50 mV, resulting in ultra-low energy consumption. A bottom-up cross-layer simulation framework is developed to synthesize and map large scale digital logic functions to the proposed STLG circuits. The simulation results of ISCAS-85 benchmarks show that the proposed STLG based reconfigurable logic hardware can achieve two orders lower Energy-Delay Product (EDP) compared with state-of-the-art CMOS Field Programmable Gate Arrays (FPGA), and smaller EDP compared to large scale Memristive Threshold Logic (MTL) based FPGA. Moreover, the ultra-low programming energy of spintronic weight device also leads to three orders lower reconfiguration energy of STLG compared to MTL design.

Delay Analysis for Current Mode Threshold Logic Gate Designs

Current mode is a popular CMOS-based implementation of threshold logic functions, where the gate delay depends on the sensor size. This paper presents a new implementation of current mode threshold functions for improved gate delay and switching energy. An analytical method is also proposed in order to identify quickly the sensor size that minimizes the gate delay. Simulation results on different gates implemented using the optimum sensor size indicate that the proposed current mode implementation method outperforms consistently the existing implementations in delay as well as switching energy.

Reducing Power, Leakage, and Area of Standard-Cell ASICs Using Threshold Logic Flip-Flops

In this paper, we describe a new approach to reduce dynamic power, leakage, and area of application-specified integrated circuits, without sacrificing performance. The approach is based on a design of threshold logic gates (TLGs) and their seamless integration with conventional standard-cell design flow. We first describe a new robust, standard-cell library of configurable circuits for implementing threshold functions. Abstractly, the threshold gate behaves as a multi-input, single-output, edge-triggered flip-flop, which computes a threshold function of the inputs on the clock edge. The library consists of a small number of cells, each of which can compute a set of complex threshold functions, which would otherwise require a multilevel network. The function realized by a given threshold gate is determined by how signals are mapped to its inputs. We present a method for the assignment of signals to the inputs of a threshold gate to realize a given threshold function. Next, we present an algorithm that replaces a subset of flip-flops and portions of their logic cones in a conventional logic netlist, with threshold gates from the library. The resulting circuits, with both conventional and TLGs (called hybrid circuits), are placed and routed using commercial tools. We demonstrate significant reductions (using postlayout simulations) in power, leakage, and area of the hybrid circuits when compared with the conventional logic circuits, when both are operated at the maximum possible frequency of the conventional design.

Implementation Aspects of Logic Functions using Single Electron Threshold Logic Gates and Hybrid SET-MOS Circuits

ABSTRACTSingle electron technology is an attractive technology for future low-power VLSI/ULSI systems. Single electronics implies the possibility to control the movement and position of a single electron or a small amount of electrons. In this work, design, implementation, and analysis of logic functions are presented using single electron threshold logic gate (TLG) and hybrid SET-MOS circuits. The logic operation of the designed circuit is tested using Monte Carlo-based simulation tool SIMON for the single electron threshold logic circuit. For the hybrid SET-MOS-based implementation, the logic operation of the circuit is verified in Tanner environment. A compact analytical model with 11 island states for SET devices and BSIM4.6.1 model for MOS is used. The influence of thermal fluctuation on the stability of the threshold logic-based circuit, caused by increase in system temperature, has been thoroughly investigated. The effect of island states on the performance of the hybrid SET-MOS circuit is analysed. Finally, the performances of both the design approaches have been analysed and compared in terms of circuit elements, voltage levels, power consumption, and delay.

Design of a novel RTD-based three-variable universal logic gate

Traditional CMOS technology faces some fundamental physical limitations. Therefore, it has become very important for the integrated circuit industry to continue to develop modern devices and new design methods. The threshold logic gate has attracted much attention because of its powerful logic function. The resonant tunneling diode (RTD) is well suited for implementing the threshold logic gate because of its high-speed switching capability, negative differential resistance (NDR) characteristic, and functional versatility. In this paper, based on the Reed-Muller (RM) algebraic system, a novel method is proposed to convert three-variable non-threshold functions to the XOR of multiple threshold functions, which is simple and has a programmable implementation. With this approach, all three-variable non-threshold functions can be presented by the XOR of two threshold functions, except for two special functions. On this basis, a novel three-variable universal logic gate (ULG3) is proposed, composed of two RTD-based universal threshold logic gates (UTLG) and an RTD-based three-variable XOR gate (XOR3). The ULG3 has a simple structure, and a simple method is presented to implement all three-variable functions using one ULG3. Thus, the proposed ULG3 provides a new efficient universal logic gate to implement RTD-based arbitrary n-variable functions.

Function Synthesis Algorithm of RTD-Based Universal Threshold Logic Gate

The resonant tunneling device (RTD) has attracted much attention because of its unique negative differential resistance characteristic and its functional versatility and is more suitable for implementing the threshold logic gate. The universal logic gate has become an important unit circuit of digital circuit design because of its powerful logic function, while the threshold logic gate is a suitable unit to design the universal logic gate, but the function synthesis algorithm for then-variable logical function implemented by the RTD-based universal logic gate (UTLG) is relatively deficient. In this paper, three-variable threshold functions are divided into four categories; based on the Reed-Muller expansion, two categories of these are analyzed, and a new decomposition algorithm of the three-variable nonthreshold functions is proposed. The proposed algorithm is simple and the decomposition results can be obtained by looking up the decomposition table. Then, based on the Reed-Muller algebraic system, the arbitraryn-variable function can be decomposed into three-variable functions, and a function synthesis algorithm for then-variable logical function implemented by UTLG and XOR2 is proposed, which is a simple programmable implementation.

Threshold Logic Computing: Memristive-CMOS Circuits for Fast Fourier Transform and Vedic Multiplication

Brain inspired circuits can provide an alternative solution to implement computing architectures taking advantage of fault tolerance and generalisation ability of logic gates. In this brief, we advance over the memristive threshold circuit configuration consisting of memristive averaging circuit in combination with operational amplifier and/or CMOS inverters in application to realizing complex computing circuits. The developed memristive threshold logic gates are used for designing FFT and multiplication circuits useful for modern microprocessors. Overall, the proposed threshold logic outperforms previous memristive-CMOS logic cells on every aspect, however, indicate a lower chip area, lower THD, and controllable leakage power, but a higher power dissipation with respect to CMOS logic.

English

The very high density of integration and ultra-low power consumption characteristics has given the Single electron devices promising capabilities to replace CMOS transistors in some applications. There are also alternative logic design styles, such as threshold logic, that may be more suitable and also more powerful for novel technologies such as single electron technology. In this paper, we investigate single electron threshold logic gate implementation of some logic circuits, in which the Boolean logic values are encoded as absence or presence of one electron. We present a control unit for a chemical process. Computer based realization of the control unit is performed using SIMON simulation tool. The performance of the simulated model is studied with some sample data and found satisfactory thereby establishing the feasibility of using single electron threshold logic based devices for high future high density low power VLSI/ULSI circuits.

Threshold Gate-Based Circuits From Nanomagnetic Logic

This paper demonstrates the design of nanomagnetic logic (NML) gates with multiple weighted inputs, which are magnetic equivalents of threshold logic gates (TLGs). We use micromagnetic simulations to show that NML TLGs can be constructed with minimum overhead compared to standard NML gates, and they significantly reduce device footprint and interconnection complexity of magnetic logic circuits. As an example, we design a full adder circuit using said TLGs and compare its performance to majority-gate-based NML.

Design and Synthesis of Ultralow Energy Spin-Memristor Threshold Logic

A threshold logic gate performs weighted sum of multiple inputs and compares the sum with a threshold. We propose spin-memristor threshold logic (SMTL) gates, which employ a memristive cross-bar array to perform current-mode summation of binary inputs, whereas the low-voltage fast-switching spintronic threshold devices carry out the threshold operation in an energy efficient manner. Field-programmable SMTL gate arrays can operate at a small terminal voltage of ~50 mV, resulting in ultralow power consumption in gates as well as programmable interconnect networks. We evaluate the performance of SMTL using threshold logic synthesis. Results for common benchmarks show that SMTL-based programmable logic hardware can be more than 100 × energy efficient than the state-of-the-art CMOS field-programmable gate array.

1-Bit Full Adder in Perpendicular Nanomagnetic Logic using a Novel 5-Input Majority Gate

In this paper, we show that perpendicular Nanomagnetic Logic (pNML) is particularly suitable to realize threshold logic gate (TLG)-based circuits. Exemplarily, a 1-bit full adder circuit using a novel 5-input majority gate based on TLGs is experimentally demonstrated. The theory of pNML and its extension by TLGs is introduced, illustrating the great benefit of pNML. Majority gates based on coupling field superposition enable weighting each input by its geometry and distance to the output. Only 5 magnets, combined in two logic gates with a footprint of 1.95 μm 2 and powered by a perpendicular clocking field, are required for operation. MFM and magneto-optical measurements demonstrate the functionality of the fabricated structure. Experimental results substantiate the feasibility and the benefits of the combination of threshold logic with pNML.

Resistive MOSFET brain-inspired threshold logic gates

The concept of a pseudo-resistive threshold logic circuit that uses a combination of CMOS inverter and bulk driven MOSFET pseudo-resistive divider circuit for designing a universal NOR gate is presented. Inspired from the neuronal firing mechanisms, the inverter implements the binary threshold decision, while pseudo-resistive circuit provides the summation of normalised weighted inputs. The proposed logic gate when tested using the TSMC 0.18 µm low voltage process show an overall improved performances in terms of area, delay and power in comparison with CMOS and pseudo NMOS logic.

Spintronic Threshold Logic Array (STLA)—A compact, low leakage, non-volatile gate array architecture

This paper describes a novel, first of its kind architecture for a threshold logic gate using conventional MOSFETs and an STT-MTJ (Spin Transfer Torque-Magnetic Tunneling Junction) device. The resulting cell, called STL which is extremely compact can be programmed to realize a large number of threshold functions, many of which would require a multilevel network of conventional CMOS logic gates. Next, we describe a novel array architecture consisting of STL cells onto which complex logic networks can be mapped. The resulting array, called STLA has several advantages not available with conventional logic. This type of logic (1) is non-volatile, (2) is structurally regular and operates like DRAM, (3) is fully observable and controllable, (4) has zero standby power. These advantages are demonstrated and compared by implementing a 16-bit carry look-ahead adder and a 32-bit Wallace tree multiplier in STLA and FPGA.

Reconfigurable Threshold Logic Gates using Memristive Devices

We present our design exploration of reconfigurable Threshold Logic Gates (TLG) implemented using silver–chalcogenide memristive devices combined with CMOS circuits. Results from simulations and physical circuits are shown. A variety of linearly separable logic functions including AND, OR, NAND, NOR have been realized in discrete hardware using a single-layer TLG. The functionality can be changed between these operations by reprogramming the resistance of the memristive devices.

Design and simulation of novel TLG–SET based RAM cell designs

In this paper, design and simulation of novel random access memory (RAM) cells using single electron tunneling (SET) technology based threshold logic gate (TLG) are presented. RAM cell designs based on RS-latch and D-latch are investigated with the aim of reducing the area, switching delay, and energy consumption. The designed circuits are simulated using Monte Carlo simulation. According to the simulation results, the circuits operations based on the transfer of single electrons between adjacent islands are stable.

Programmable CMOS/Memristor Threshold Logic

This paper proposes a hybrid CMOS/memristor implementation of a programmable threshold logic gate. In this gate, memristive devices implement ratioed diode-resistor logic, while CMOS circuitry is used for signal amplification and inversion. Due to the excellent scaling prospects and nonvolatile analog memory of memristive devices, the proposed threshold logic is in-field configurable and potentially very compact. The concept is experimentally verified by implementing a 4-input symmetric linear threshold gate with an integrated circuit CMOS flip-flop, silicon diodes, and Ag/a-Si/Pt memristive devices.

Design and Simulation of Single Electron Threshold Logic Gate based Programmable Logic Array

Single electron tunnelling technology based threshold logic gate is one of the basic functional blocks for designing single electronics circuits. In this paper design and implementation of threshold logic gates based Programmable logic array is presented. The logic operation of the circuit is simulated using well accepted Monte Carlo based simulation tool SIMON. The stability of the designed circuit is analysed using stability plots. Here the stability has been analysed considering different input combinations of the designed circuit.

Novel Practical Built-in Current Sensors

In this paper, we propose three new built-in current sensors (BICS) topologies for on-chip IDDQ tests of analog/mixed-signal (AMS) circuits with the objective to achieve low design complexity, small area overhead and high accuracy. The first two approaches are derived from digital varicap threshold logic (VcTL) gate idea where the structure is modified for analog inputs. The third approach is a switched-cap (SC) methodology with a latch type comparator. Each design and corresponding performance results are provided in details and verified with corner and Monte Carlo analyses. All three approaches are designed as both ATE-assisted and built-in self-test (BIST) solutions. Low drop-out regulators (LDOs) in an AMS system on-chip (SOC) having more than 20 LDOs are selected as circuit under tests (CUT). The target current range is 0–100 μA to cover all LDOs. Moreover, the programmability of these proposed BICS provide a single BICS per chip solution. The overall IDDQ test time is reduced from 927 μs to 280 ns by using proposed BICS (VcTL type with PMOS capacitances). It is a significant improvement in test time and cost considering that the sensor only occupies 0.36 % of a single LDO area or equivalently 0.02 % of entire LDO subsystem.

Design and simulation of novel TLG–SET based configurable logic cells

Single electron tunneling circuits seem to be promising candidates as basic circuit elements of the next generation ultra-dense VLSI and ULSI circuits for their ultra-low power consumption, ultra-small size, and rich functionality. In this paper, design and simulation of novel configurable logic cells (CLCs) using single electron tunneling (SET) technology based threshold logic gate (TLG) are presented. The proposed CLC can realize all Boolean logic functions by configuring the control bits without changing the structure of the circuit and the parameters of TLG–SET based design. The logic operation of the circuit is simulated using Monte Carlo simulation. According to the simulation results, the circuit operation based on the transfer of single electrons between adjacent islands is stable.