Threshold Logic Gates Research Articles

A threshold logic gate based on clocked coupled inverters

In this paper we present both a new design for a threshold logic gate, based on clocked cross-coupled inverters, and the way to optimize the implementation of threshold functions using this gate. The main characteristics of the threshold gate are low power consumption (it does not consume static power) and high speed.

A capacitive threshold-logic gate

A dense and fast threshold-logic gate with a very high fan-in capacity is described. The gate performs sum-of-product and thresholding operations in an architecture comprising a poly-to-poly capacitor array and an inverter chain. The Boolean function performed by the gate is soft programmable. This is accomplished by adjusting the threshold with a dc voltage. Essentially, the operation is dynamic and thus, requires periodic reset. However, the gate can evaluate multiple input vectors in between two successive reset phases because evaluation is nondestructive. Asynchronous operation is, therefore, possible. The paper presents an electrical analysis of the gate, identifies its limitations, and describes a test chip containing four different gates of fan-in 30, 62, 127, and 255. Experimental results confirming proper functionality in all these gates are given, and applications in arithmetic and logic function blocks are described.

A compact high-speed (31,5) parallel counter circuit based on capacitive threshold-logic gates

A novel high-speed circuit implementation of the (31,5)-parallel counter (i.e., population counter) based on capacitive threshold logic (CTL) is presented. The circuit consists of 20 threshold logic gates arranged in two stages, i.e., the parallel counter described here has an effective logic depth of two. The charge-based CTL gates are essentially dynamic circuits which require a periodic refresh or precharge cycle, but unlike conventional dynamic CMOS gates, the circuit can be operated in synchronous as well as in asynchronous mode. The counter circuit is implemented using conventional 1.2 /spl mu/m double-poly CMOS technology, and it occupies a silicon area of about 0.08 mm/sup 2/. Extensive post-layout simulations indicate that the circuit has a typical input-to-output propagation delay of less than 3 ns, and the test circuit is shown to operate reliably when consecutive 31-b input vectors are applied at a rate of up to 16 Mvectors/s. With its demonstrated data processing capability of about 500 Mb/s, the CTL-based (31,5) parallel counter offers a number of application possibilities, e.g., in high-speed parallel multiplier arrays and data encoding circuits.

Low-power CMOS threshold-logic gate

A new implementation of a threshold gate based on a latch-type comparator that does not consume static power is presented. Simulation results indicate high operation speed and low power consumption, which make it very attractive when used as a basic building block in digital design.

Optimization of NbN MVTL logic gates for 10 K operation

We have systematically studies designs for Modified Variable Threshold Logic Gates (MVTL) in NbN within the framework of factorial analysis. Our goal is to attain optimized margin and fanout for 10 K operation. Significant parasitic inductances, associated with current crowding at junction vias, were measured and are found to affect the operating margin. We report the progression of designs, margin measurements and yield data for our 10 K circuits. >

Permutation weighted order statistic filter lattices

We introduce and analyze a new class of nonlinear filters called permutation weighted order statistic (PWOS) filters. These filters extend the concept of weighted order statistic (WOS) filters, in which filter weights associated with the input samples are used to replicate the corresponding samples, and an order statistic is chosen as the filter output. PWOS filters replicate each input sample according to weights determined by the temporal-order and rank-order of samples within a window. Hence, PWOS filters are in essence time-varying WOS filters. By varying the amount of temporal-rank order information used in selecting the output for a given observation window size, we obtain a wide range of filters that are shown to comprise a complete lattice structure. At the simplest level in the lattice, PWOS filters reduce to the well-known WOS filter, but for higher levels in the lattice, the obtained selection filters can model complex nonlinear systems and signal distortions. It is shown that PWOS filters are realizable by a N! piecewise linear threshold logic gate where the coefficients within each partition can be easily optimized using stack filter theory. Simulations are included to show the advantages of PWOS filters for the processing of image and video signals.

Niobium based Josephson circuit technology

Abstract Since the introduction of reliable niobium junctions, Josephson circuit technology has made remarkable progress. We have demonstrated high speed Josephson circuits such as a 4-bit microprocessor and an 8-bit digital signal processor. In this paper, we describe key technologies to realize these circuits, mainly from the viewpoint of circuit design. One of them is the high speed modified variable threshold logic (MVTL) gates which have a large operating margin and high sensitivity. Another is the three-phase ac power system. This power method requires no latching circuits, making the circuitry very simple and resulting in high speed operation. For designing large scale circuits, a systematic design method is also important. Josephson logic has latching characteristics and requires alternate current supply that is quite different from semiconductor logic. We modified existing tools for semiconductor circuits and established a new design system. We also introduced scan path registers for testing the circuit. Using two scan path registers, one at the input and one at the output, we demonstrated RAM read out operation.

A voltage tunable threshold logic gate based on multiquantum-well heterojunction bipolar transistor for multifunction logic

The properties of a heterojunction bipolar transistor with a multiquantum-well collector region for its application as a voltage tunable logic element are examined. The quantum confined Stark effect gives rise to a strong negative differential resistance in the photocurrent-voltage characteristic of the device, which allows the device to be switched optically and/or electronically. This permits the realization of a circuit where the NAND, INVERSE CARRY, and NOR logic functions can be implemented by simply changing the biasing.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

High-speed Josephson integrated circuit technology

The author describes recent progress in high-speed integrated circuits using niobium junctions. He briefly describes the circuit fabrication process and then introduces the modified variable threshold logic (MVTL) gate family. The lowest experimentally obtained MVTL OR-gate delay was only 2.5 ps with a power consumption of 17 mu W/gate. This gate family is used in various high-speed logic circuits, such as 8-bit shift registers, 16-bit ALUs (arithmetic logic units), and 4-bit microprocessors. The author confirmed the high-speed operation of less than 10 ps per gate on average for these circuits. A novel high-sensitivity magnetic sensor using a SQUID (superconducting quantum interference device) was also developed. It is called a single-chip SQUID magnetometer because the feedback circuit, which is operated at room temperature is a conventional SQUID system, has been integrated on the same chip as the SQUID sensor itself.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Logical Signal Processing With Optically Connected Threshold Gates

The characteristic features of deterministic and nondeterministic optical threshold logic gates are reviewed. Analog, binary, multiple-valued, multiple-class, and polynomial threshold gates are considered. Threshold synthesis techniques are outlined. Bulk optical and integrated optical implementations of reconfigurable threshold gates are discussed. Examples of deterministic logic operations involving binary addition and digital picture processing are presented. Applications to nondeterministic operations such as pattern recognition and heteroassociative processing are considered. The sensitivity of deterministic and nondeterministic mul-tiple-input optical threshold gates to physical errors is analyzed. The particular advantages of optically connected threshold gates with respect to electronic threshold gates are discussed.

A four-variable programmable universal logic module using digital summation threshold logic gates

Combining the concepts of programmable logic arrays (PLAs) and conventional universal logic modules (ULMs) a new type of programmable ULM for four variables has been proposed. The realization is based on the digital summation threshold logic (DSTL) gates, a cellular array for realizing threshold logic functions.

Logic design using digital summation threshold-logic gates

The advent of IC technology has resulted in the fabrication of IC threshold gates which are competitive, both in performance and cost with standard logic packages. Of them, the multioutput digital summation threshold-logic (DSTL) gate is considered to be a potential candidate of future interest. In this paper, an algorithm has been developed to realise nonthreshold functions utilising the multioutput capability of DSTL gates. In this context, optimal realisation has been discussed. An universal logic module (ULM) has been proposed, based on DSTL approach, and an optimised structure of ULM for 4-variable functions is suggested.

Circuits for quaternary-to-analogue conversion†

Digital-to-analogue (D/A) and analogue-to-digital (A/D) converters play incresingly important rules in modern signal processing due to increasingly affordable ami available (binary) digital integrnted circuits. Research into multiple-valued logic (MVL) indicates that in many situations MVL can be more efficient and effective than binary logic. As the use of MVL in digital systems increases and evolves, the MVL counterpart of A/D and D/A conversion will be required. In this paper active and passive circuits for the conversion of quaternary logic signals into analogue waveforms nrc presented. These circuits are compatible with previously reported quaternary threshold logic gates.

Realisation of multithreshold threshold-logic gates using charge-coupled devices

A threshold logic gate is described which uses as its core a charge-coupled device. It is shown that the CCD is suitable for this application because of its ability to (a) quantise charge input to a gate, (b) add charge packets from different gates, and (c) permit conditional charge overflow to occur. The peripheral circuitry employs compatible MOSFET circuits, so that the entire gate can be made in integrated circuit form. The gate is voltage programmbale.

Realisation of logic functions by multi-output threshold-logic gates

Two different multi-output threshold-logic gate structures are considered and their information requirements compared. A method, based on a trial and error algorithm, is described which may be used to realise a logic function by each of these structures. The method is quite general and has been tested on a large number of functions. Some preliminary observations from these tests are presented.

Complex Number Arithmetic with Odd- Valued Logic

Digital signal processing such as discrete Fourier transform requires complex number arithmetic. Number-theoretical properties favor odd-radix systems for simple implementation of complex number operations. An array ternary complex multiplier is presented and compared to other complex multipliers. As an illustration, a perfectly balanced ternary system is implemented by means of current-mode threshold logic gates.

Improvements in multioutput threshold-logic gates

Previous developments by Winn (1975) on the design of single-output threshold-logic gates using Boolean product-of-sum expansions have been extended to the consideration of multioutput threshold-logic gates, by searching for optimum factorising of Winn functions to provide common terms for dissimilar threshold outputs. It has been found that such searches do not yield good results, but the combination of Winn plus parity functions is more viable. A need for more powerful digital synthesis techniques to handle multioutput design, with the ability to choose the number of logic levels per realisation, is found to be desirable for this and all other multioutput design problems.

Some improved designs for the digital summation threshold logic (DSTL) gate

Some improved designs for the digital summation threshold logic (DSTL) gate

Programmable Circuit to Identify Signal Arrival Order

A simple circuit, using a counter, to identify the signal which arrives in a particular place in the arrival order is described. It uses off-the-shelf components, without need for threshold logic gates, and avoids the complexity of the circuits using vertex gates. The circuit is programmable and can easily be extended to more number of inputs. It finds application in a variety of fields.

Threshold-logic instrumentation to identify the signal-arrival order

A circuit which resolves a group of binary signals and identifies the order in which they arrive is described. A digital summation threshold-logic (DSTL) gate, having multithreshold outputs is made use of to realize the required logic of the circuit presented.