Novel Practical Built-in Current Sensors

Abstract

In this paper, we propose three new built-in current sensors (BICS) topologies for on-chip IDDQ tests of analog/mixed-signal (AMS) circuits with the objective to achieve low design complexity, small area overhead and high accuracy. The first two approaches are derived from digital varicap threshold logic (VcTL) gate idea where the structure is modified for analog inputs. The third approach is a switched-cap (SC) methodology with a latch type comparator. Each design and corresponding performance results are provided in details and verified with corner and Monte Carlo analyses. All three approaches are designed as both ATE-assisted and built-in self-test (BIST) solutions. Low drop-out regulators (LDOs) in an AMS system on-chip (SOC) having more than 20 LDOs are selected as circuit under tests (CUT). The target current range is 0–100 μA to cover all LDOs. Moreover, the programmability of these proposed BICS provide a single BICS per chip solution. The overall IDDQ test time is reduced from 927 μs to 280 ns by using proposed BICS (VcTL type with PMOS capacitances). It is a significant improvement in test time and cost considering that the sensor only occupies 0.36 % of a single LDO area or equivalently 0.02 % of entire LDO subsystem.