Three-dimensional Integration Research Articles

3차원 집적 유연 인쇄 전자: 집적 회로, 메모리, 센서

Printing technologies have received a lot of attention and expectations for producing flexible and wearable electronics. However, the low transistor density of the printed devices has been a major obstacle to commercialization. In this review, a three-dimensional (3D) integration of organic flexible and printed electronics is described. First, layout-to-bitmap conversion and design rules for printed transistors, arrays, and integrated circuits are introduced. Then, printed 3D transistors, digital integrated circuits, and memories are described. Finally, 3D integration of printed active-matrix arrays and sensors is highlighted. This approach is a breakthrough technology that not only reduces the area occupied by a single transistor, memory, and sensor, but also increases the efficiency of routing, effectively reducing the area of the entire devices. In addition, monolithic 3D integration through the printing can stack transistor, memory, and sensor by simply repeating the additive process.

Atomic and electronic origin of robust off-state insulation properties in Al-rich AlxTey glass for ovonic threshold switching applications

Ovonic threshold switching (OTS) selectors play a critical role in suppressing the sneak-path current of three-dimensional crossbar integration circuits. Compared to conventional nonmetal-telluride OTS selectors, selectors based on AlxTey glass are found to have both satisfactory on-state current and selectivity. However, it is unclear why the Al-rich AlxTey glass-based OTS selectors have robust insulation properties for reducing the off-state current. This work reveals the structure–property correlations of amorphous AlxTey at the atomic scale by first-principles calculations. It is found that the stoichiometric Al2Te3 glass tends to have a clean bandgap owing to the covalent and dative bonds formed by non-equivalent sp3-hybridized Al orbitals and the lone-pair electrons of Te. Unexpectedly, for Al-rich AlxTey glass (Al2.21Te2.79), the Al–Al bonds formed by redundant Al-atoms have an integrated crystal orbital bond index (ICOBI) of 0.8–0.9, which is much larger than that of Al–Al bonds in pure metals (0.227), indicating they are covalent. It is the covalent Al–Al bonds that ensure the robust insulation characteristics of Al-rich AlxTey glass, while the Te–Te interaction in the Al-poor AlxTey glass (Al1.79Te3.21) produces midgap states, thereby reducing the insulativity. The presented atomic and electronic pictures here will provide useful theoretical insights for designing OTS selectors with improved performances.

Micr -Transfer Printing for Efficient 3DHI of 100-300mm Wafers and Glass Panels

This paper presents an analysis of using micro-transfer printing (MTP) for three-dimensional heterogeneous integration (3DHI) of diverse components made using 100mm, 200mm and 300mm wafers with large area glass substrates. Techniques for achieving high throughput and high wafer and substrate utilization, despite their size mis-matches, are described in detail along with MTP’s pros and cons versus alternative wafer-to-wafer and die-to-wafer 3DHI technologies. MTP, a massively parallel pick-and-place process, efficiently transfers large arrays of ultra-thin (<10 micron), small, diverse components (“x-chips”) from one or more source wafers to destination substrates. MTP enables disruptive 3DHI of compound semiconductors, including GaN, GaAs, InP, SiGe and emerging materials, silicon and passive components for wireless and optical communications, power management, sensor, photonics and other analog / mixed signal applications. Since the x-chips are ultra-thin and active side up, standard copper redistribution layer (RDL) technology may be readily used to interconnect the x-chips and destination die, resulting in very short path lengths and, hence, minimum parasitics. ASM AMICRA and X Display Company supply R&D and production MTP manufacturing systems. More than twenty MTP systems are installed worldwide at X-FAB, Micross Components, Tyndall National Institute, Teledyne, the Naval Research Laboratory, the University of Illinois Urbana Champaign, the University of Ghent / imec, UPVfab and undisclosed leading manufacturers.

Monolithic three-dimensional integration of RRAM-based hybrid memory architecture for one-shot learning

In this work, we report the monolithic three-dimensional integration (M3D) of hybrid memory architecture based on resistive random-access memory (RRAM), named M3D-LIME. The chip featured three key functional layers: the first was Si complementary metal-oxide-semiconductor (CMOS) for control logic; the second was computing-in-memory (CIM) layer with HfAlOx-based analog RRAM array to implement neural networks for feature extractions; the third was on-chip buffer and ternary content-addressable memory (TCAM) array for template storing and matching, based on Ta2O5-based binary RRAM and carbon nanotube field-effect transistor (CNTFET). Extensive structural analysis along with array-level electrical measurements and functional demonstrations on the CIM and TCAM arrays was performed. The M3D-LIME chip was further used to implement one-shot learning, where ~96% accuracy was achieved on the Omniglot dataset while exhibiting 18.3× higher energy efficiency than graphics processing unit (GPU). This work demonstrates the tremendous potential of M3D-LIME with RRAM-based hybrid memory architecture for future data-centric applications.

Wafer-scale organic-on-III-V monolithic heterogeneous integration for active-matrix micro-LED displays.

The organic thin-film transistor is advantageous for monolithic three-dimensional integration attributed to low temperature and facile solution processing. However, the electrical properties of solution deposited organic semiconductor channels are very sensitive to the substrate surface and processing conditions. An organic-last integration technology is developed for wafer-scale heterogeneous integration of a multi-layer organic material stack from solution onto the non-even substrate surface of a III-V micro light emitting diode plane. A via process is proposed to make the via interconnection after fabrication of the organic thin-film transistor. Low-defect uniform organic semiconductor and dielectric layers can then be formed on top to achieve high-quality interfaces. The resulting organic thin-film transistors exhibit superior performance for driving micro light emitting diode displays, in terms of milliampere driving current, and large ON/OFF current ratio approaching 1010 with excellent uniformity and reliability. Active-matrix micro light emitting diode displays are demonstrated with highest brightness of 150,000 nits and highest resolution of 254 pixels-per-inch.

Monolithic 3D Integration of Analog RRAM-Based Computing-in-Memory and Sensor for Energy-Efficient Near-Sensor Computing.

In the era of the Internet of Things, vast amounts of data generated at sensory nodes impose critical challenges on the data-transfer bandwidth and energy efficiency of computing hardware. A near-sensor computing (NSC) architecture places the processing units closer to the sensors such that the generated data can be processed almost in situ with high efficiency. This study demonstrates the monolithic three-dimensional (M3D) integration of a photosensor array, analog computing-in-memory (CIM), and Si complementary metal-oxide-semiconductor (CMOS) logic circuits, named M3D-SAIL. This approach exploits the high-bandwidth on-chip data transfer and massively parallel CIM cores to realize an energy-efficient NSC architecture. The 1st layer of the Si CMOS circuits serves as the control logic and peripheral circuits. The 2nd layer comprises a 1k-bit one-transistor-one-resistor (1T1R) array with InGaZnOx field-effect transistor (IGZO-FET) and resistive random-access memory (RRAM) for analog CIM. The 3rd layer comprises multiple IGZO-FET-based photosensor arrays for wavelength-dependent optical sensing. The structural integrity and function of each layer are comprehensively verified. Furthermore, NSC is implemented using the M3D-SAIL architecture for a typical video keyframe-extraction task, achieving a high classification accuracy of 96.7% as well as a 31.5× lower energy consumption and 1.91× faster computing speed compared to its2D counterpart.

Characterization of melanoidins in thermal hydrolysis sludge and effects on dewatering performance

Thermal hydrolysis pretreatment (THP) of sludge can form the refractory brown melanoidins due to the occurrence of the Maillard reaction, which adversely involves the subsequent sludge anaerobic digestion (AD) process. However, details of the generation pattern of melanoidins and how they affect the sludge dewaterability remain largely unknown. This work aims to determine an approach to characterize and quantify the melanoidins created by THP of sludge. On this basis, the effect of melanoidins on sludge dewatering performance was revealed by adding synthetic melanoidins to the mixed sludge. Experimental results showed that three-dimensional fluorescence-region integration (3DEEM-FRI) could effectively distinguish melanoidins from other organic substances and achieve semi-quantitative characterization in sludge. The melanoidins significantly deteriorated the sludge dewaterability, and the lowest solids content of the filter cake (TS) was only 17.78% at the addition of 480 mg (g TS)-1, which was a drop of about 20% compared to the control group. The mechanism investigations indicated that the internal structure of sludge becoming particularly complicated and the opportunities for molecules to collide with each other enlarged because of the contribution of melanoidins, resulting in the increment of the sludge apparent viscosity and consistency coefficient (k), a decline of the flow behavior index (n) and a weakening of flowability. Melanoidins could capture massive water molecules and carry negative charges with the decrease of sludge particle size and zeta potential value, which enhanced the electrostatic repulsion between sludge particles and abated the flocculation ability, thus further aggravating the sludge dewatering performance.

A Three-Dimensional Triangle Mesh Integration Method for Oblique Photography Model Data

Oblique photography 3D models are increasingly used in 3D modeling and visualization, urban planning and design, smart cities, smart mines, and other fields. To ensure that 3D models can be replaced and updated, it is necessary to deal with the model holes and incomplete areas caused by the incorrect matching of feature points in the modeling process. Moreover, in 3D models of the planning and management of certain mining areas or urban areas to be developed, regions can also be delineated for replacements and updates. Due to the unsatisfactory display effect of the manually modeled models used to replace and update, the authenticity of the model texture and the detail characteristics of the model triangle meshes cannot be guaranteed during integration. Therefore, this paper proposes a 3D model triangle mesh integration method for oblique photography data which integrates the real and complete 3D models used for replacement with the incomplete part or the part of the original model that needs to be replaced. The experimental results show that this method can integrate the original terrain model and the replacement model efficiently and quickly, the integrated model has no gap, and the display effect is good, effectively achieving model repair or model update and replacement.

Three-Dimensional Integration of Switching and Light-Sensitive Organic Transistors in Solution Processes for Flexible High-Resolution Active-Matrix Optical Imager

Three-Dimensional Integration of Switching and Light-Sensitive Organic Transistors in Solution Processes for Flexible High-Resolution Active-Matrix Optical Imager

3D integration enables ultralow-noise isolator-free lasers in silicon photonics

Photonic integrated circuits are widely used in applications such as telecommunications and data-centre interconnects1–5. However, in optical systems such as microwave synthesizers6, optical gyroscopes7 and atomic clocks8, photonic integrated circuits are still considered inferior solutions despite their advantages in size, weight, power consumption and cost. Such high-precision and highly coherent applications favour ultralow-noise laser sources to be integrated with other photonic components in a compact and robustly aligned format—that is, on a single chip—for photonic integrated circuits to replace bulk optics and fibres. There are two major issues preventing the realization of such envisioned photonic integrated circuits: the high phase noise of semiconductor lasers and the difficulty of integrating optical isolators directly on-chip. Here we challenge this convention by leveraging three-dimensional integration that results in ultralow-noise lasers with isolator-free operation for silicon photonics. Through multiple monolithic and heterogeneous processing sequences, direct on-chip integration of III–V gain medium and ultralow-loss silicon nitride waveguides with optical loss around 0.5 decibels per metre are demonstrated. Consequently, the demonstrated photonic integrated circuit enters a regime that gives rise to ultralow-noise lasers and microwave synthesizers without the need for optical isolators, owing to the ultrahigh-quality-factor cavity. Such photonic integrated circuits also offer superior scalability for complex functionalities and volume production, as well as improved stability and reliability over time. The three-dimensional integration on ultralow-loss photonic integrated circuits thus marks a critical step towards complex systems and networks on silicon.

Feasibility of three-dimensional artificial intelligence algorithm integration with intracardiac echocardiography for left atrial imaging during atrial fibrillation catheter ablation.

Intracardiac echocardiography (ICE) is a useful but operator-dependent tool for left atrial (LA) anatomical rendering during atrial fibrillation (AF) ablation. The CARTOSOUND FAM Module, a new deep learning (DL) imaging algorithm, has the potential to overcome this limitation. This study aims to evaluate feasibility of the algorithm compared to cardiac computed tomography (CT) in patients undergoing AF ablation. In 28 patients undergoing AF ablation, baseline patient information was recorded, and three-dimensional (3D) shells of LA body and anatomical structures [LA appendage/left superior pulmonary vein/left inferior pulmonary vein/right superior pulmonary vein/right inferior pulmonary vein (RIPV)] were reconstructed using the DL algorithm. The selected ultrasound frames were gated to end-expiration and max LA volume. Ostial diameters of these structures and carina-to-carina distance between left and right pulmonary veins were measured and compared with CT measurements. Anatomical accuracy of the DL algorithm was evaluated by three independent electrophysiologists using a three-anchor scale for LA anatomical structures and a five-anchor scale for LA body. Ablation-related characteristics were summarized. The algorithm generated 3D reconstruction of LA anatomies, and two-dimensional contours overlaid on ultrasound input frames. Average calculation time for LA reconstruction was 65 s. Mean ostial diameters and carina-to-carina distance were all comparable to CT without statistical significance. Ostial diameters and carina-to-carina distance also showed moderate to high correlation (r = 0.52-0.75) except for RIPV (r = 0.20). Qualitative ratings showed good agreement without between-rater differences. Average procedure time was 143.7 ± 43.7 min, with average radiofrequency time 31.6 ± 10.2 min. All patients achieved ablation success, and no immediate complications were observed. DL algorithm integration with ICE demonstrated considerable accuracy compared to CT and qualitative physician assessment. The feasibility of ICE with this algorithm can potentially further streamline AF ablation workflow.

Iterative approaches for regional Moho determination using on-orbit gravity gradients: A case study in Qinghai-Tibet Plateau and its near zone

Summary Moho determination is an important issue in studying the Earth’s interior structure. In accordance with the isostasy-compensation hypothesis in geodesy, it is possible to recover regional or global Moho by employing gravimetric data. The non-linear property is one of the main difficulties in solving the inverse problem of isostasy. To effectively address this issue, we propose an improved iterative inversion method that combines three-dimensional integration and linear regularization to achieve an approximate non-linear solution. To estimate the contributions of different components in the gravity-gradient tensor from the Gravity field and steady-state Ocean Circulation Explorer (GOCE), other than the vertical component, we additionally develop two joint inversion scenarios that utilize diagonal horizontal components and all five non-vertical components. The validating experiments are implemented in Qinghai-Tibet Plateau and its near zone. Simulations and applications illustrate that horizontal responses of Moho undulation are also significant. Yet the off-diagonal components provide minimal contributions, adding only 0.25 km of bias to the joint inversion results. Truncation effects serve as the primary source of systematic errors, resulting in ∼1 km error in vertical inversion results and ∼2.3 km error in joint inversion results. Then, the gravimetric Moho results are compared with CRUST1.0, and they show a generally strong correlation. Differences are obvious at the northern and eastern margins of the plateau. It is maybe due to the local changes in crust-mantle density contrasts. Upwelling of asthenospheric materials and fluid flow in the middle-lower crust are the two main factors. Based on high-precision satellite gravimetry, our study could provide new insights into the tectonic structure of Qinghai-Tibet Plateau.

Research of Vertical via Based on Silicon, Ceramic and Glass.

With the increasing demand for high-density integration, low power consumption and high bandwidth, creating more sophisticated interconnection technologies is becoming increasingly crucial. Three-dimensional (3D) integration technology is known as the fourth-generation packaging technology beyond Moore's Law because of its advantages of low energy consumption, lightweight and high performance. Through-silicon via (TSV) is considered to be at the core of 3D integration because of its excellent electrical performance, lower power consumption, wider bandwidth, higher density, smaller overall size and lighter weight. Therefore, the particular emphasis of this review is the process flow of TSV technology. Among them, the research status of TSV hole etching, deep hole electroplating filling and chemical mechanical planarization (CMP) in TSV preparation process are introduced in detail. There are a multitude of inevitable defects in the process of TSV processing; thus, the stress problems and electrical characteristics that affect the reliability of TSV are summarized in this review. In addition, the process flow and process optimization status of through ceramic via (TCV) and through glass via (TGV) are discussed.

Design of a Novel Compact Bandpass Filter Based on Low-Cost Through-Silicon-Via Technology.

Three-dimensional (3D) integration based on through-silicon-via (TSV) technology provides a solution to the miniaturization of electronic systems. In this paper, novel integrated passive devices (IPDs) including capacitor, inductor, and bandpass filter are designed by employing TSV structures. For lower manufacturing costs, polyimide (PI) liners are used in the TSVs. The influences of structural parameters of TSVs on the electrical performance of the TSV-based capacitor and inductor are individually evaluated. Moreover, with the topologies of capacitor and inductor elements, a compact third-order Butterworth bandpass filter with a central frequency of 2.4 GHz is developed, and the footprint is only 0.814 mm × 0.444 mm. The simulated 3-dB bandwidth of the filter is 410 MHz, and the fraction bandwidth (FBW) is 17%. Besides, the in-band insertion loss is less than 2.63 dB, and the return loss in the passband is better than 11.4 dB, showing good RF performance. Furthermore, as the filter is fully formed by identical TSVs, it not only features a simple architecture and low cost, but also provides a promising idea for facilitating the system integration and layout camouflaging of radio frequency (RF) devices.

Recent progress of photodetector based on carbon nanotube film and application in optoelectronic integration

Due to its remarkable electrical and optical capabilities, optoelectronic devices based on the semiconducting single-walled carbon nanotube (s-SWCNT) have been studied extensively in the last two decades. First, s-SWCNT is a direct bandgap semiconductor with a high infrared absorption coefficient and high electron/hole mobility. In addition, as a typical one-dimensional material, there is no lattice mismatch between s-SWCNT and any substrates. Another advantage is that the optoelectronic devices of s-SWCNT can be processed at low temperatures. S-SWCNT has intriguing potential and applications in solar cells, light-emitting diodes (LEDs), photodetectors, and three-dimensional (3D) optoelectronic integration. In recent years, along with the advancement of solution purification technology, the high-purity s-SWCNTs film has laid the foundation for constructing large-area, homogenous, and high-performance optoelectronic devices. In this review, optoelectronic devices based on s-SWCNTs film and related topics are reviewed, including the preparation of high purity s-SWCNTs film, the progress of photodetectors based on the s-SWCNTs film, and challenges of s-SWCNTs film photodetectors.

Monolithic Three-Dimensional Integration of Carbon Nanotube Circuits and Sensors for Smart Sensing Chips.

Semiconducting carbon nanotube (CNT) film is a promising material for constructing high-performance complementary metal-oxide-semiconductor (CMOS) integrated circuits (ICs) and highly sensitive field-effect transistor (FET) bio/chemical sensors. Moreover, CNT logic transistors and sensors can be integrated through a compatible low-temperature fabrication process, providing enough thermal budget to construct monolithic three-dimensional (M3D) systems for smart sensors. However, an M3D sensing chip based on CNT film has not yet been demonstrated. In this work, we develop M3D technology to fabricate CNT CMOS ICs and CNT sensor arrays in two different layers; then, we demonstrate a preliminary M3D sensing system comprising CNT CMOS interfacing ICs in the bottom layer and CNT sensors in the upper layer through interlayer vias as links. As a typical example, a highly sensitive hydrogen sensing IC has been demonstrated to perform in situ sensing and processing functions through upper-layer FET-based hydrogen sensors exposed to the environment and bottom-layer CNT CMOS voltage-controlled oscillator (VCO) interfacing circuits. The M3D CNT sensing ICs convert hydrogen concentration information (8-128 ppm) to digital frequency information (0.78-1.11 GHz) with a sensitivity of 2.75 MHz/ppm. M3D sensing technology is expected to provide a universal sensing system for future smart sensing chips, including multitarget detection and ultralow power sensors.

Three-Dimensional Integration of InAs Nanowires by Template-Assisted Selective Epitaxy on Tungsten.

3D integration of III-V semiconductors with Si CMOS is highly attractive since it allows combining new functions such as photonic and analog devices with digital signal processing circuitry. Thus far, most 3D integration approaches have used epitaxial growth on Si, layer transfer by wafer bonding, or die-to-die packaging. Here we present low-temperature integration of InAs on W using Si3N4 template assisted selective area metal-organic vapor-phase epitaxy (MOVPE). Despite growth nucleation on polycrystalline W, we can obtain a high yield of single-crystalline InAs nanowires, as observed by transmission electron microscopy (TEM) and electron backscatter diffraction (EBSD). The nanowires exhibit a mobility of 690 cm2/(V s), a low-resistive, Ohmic electrical contact to the W film, and a resistivity which increases with diameter attributed to increased grain boundary scattering. These results demonstrate the feasibility for single-crystalline III-V back-end-of-line integration with a low thermal budget compatible with Si CMOS.

Scalable CMOS back-end-of-line-compatible AlScN/two-dimensional channel ferroelectric field-effect transistors.

Three-dimensional monolithic integration of memory devices with logic transistors is a frontier challenge in computer hardware. This integration is essential for augmenting computational power concurrent with enhanced energy efficiency in big data applications such as artificial intelligence. Despite decades of efforts, there remains an urgent need for reliable, compact, fast, energy-efficient and scalable memory devices. Ferroelectric field-effect transistors (FE-FETs) are a promising candidate, but requisite scalability and performance in a back-end-of-line process have proven challenging. Here we present back-end-of-line-compatible FE-FETs using two-dimensional MoS2 channels and AlScN ferroelectric materials, all grown via wafer-scalable processes. A large array of FE-FETs with memory windows larger than 7.8 V, ON/OFF ratios greater than 107 and ON-current density greater than 250 μA um-1, all at ~80 nm channel length are demonstrated. The FE-FETs show stable retention up to 10 years by extension, and endurance greater than 104 cycles in addition to 4-bit pulse-programmable memory features, thereby opening a path towards the three-dimensional heterointegration of a two-dimensional semiconductor memory with silicon complementary metal-oxide-semiconductor logic.

An implicit 3D nodal integration based PFEM (N-PFEM) of natural temporal stability for dynamic analysis of granular flow and landslide problems

The particle finite element method (PFEM) is a robust approach for modelling large deformation problems with free surface evolution. The classical PFEM, however, requires variable mapping from old to new quadrature points when adopting history-dependent material models in granular flow and landslide problems. Although the nodal integration technique circumvents this issue, it makes the PFEM temporal instable in dynamic analysis when using a displacement-based formulation. In this study, we developed a new version of a three-dimensional (3D) Nodal integration based PFEM (N-PFEM) using a mixed variational principle with the final problem resolved in mathematical programming. The proposed N-PFEM not only inherits the benefit from the nodal integration scheme that no variable mapping is required for handling history-dependent models but also is naturally temporal stable requiring no ad-hoc stabilization technique. We simulated a series of benchmark problems to demonstrate its nature of temporal stability as well as other admirable features such as the volumetric-locking free property and capability for tackling extreme configuration changes. Additionally, its application to a 3D landslide with a sensitive clay layer is shown to highlight its robustness.

Flash memory hole etch profile monitoring using x-ray and optical scatterometry

Memory hole (MH) etching may be one of the most critical and challenging processes in three-dimensional flash processing and integration. As the holes get deep, hole critical dimensions (CDs) can vary significantly during the top-down etch processing, the hole shape can deviate from a round hole, and the centerline of the hole can deviate from a vertical line. These and other complex behaviors depend on not only the process conditions (chemistry, plasma power, bias, temperature, etc.) but also the process chamber history [e.g., radio frequency (RF) hours from preventative maintenance] and how the process chambers are conditioned. In addition, the etch behavior depends on the tier thickness (ONON or OPOP), materials, deposition conditions, and overall wafer topography and shapes. The etch behavior is further related to the die positions on the wafer (center or middle versus edge dies) and the position in the memory cell (close to the edge of the cell or near the center of the cell). To monitor and control the etch behavior, many metrology methods have been developed; these include the etch-back top-view scanning electron microscopy (SEM), tilt SEM, transmission electron microscopy (TEM), and high voltage scanning electron microscopy (HVSEM). These methods are time consuming, and some are destructive, but they have been deemed the ground truth for determining variations in MH etch processes. We report a methodology that combines optical scatterometry (SCD) and small-angle x-ray scatterometry measurements to provide reliable CD profile measurements while meeting the fast-turnaround sampling requirements of high-volume manufacturing.