Three-dimensional Chip Stacking Research Articles

Lattice Boltzmann modeling of heat conduction enhancement by colloidal nanoparticle deposition in microporous structures.

Drying of colloidal suspension towards the exploitation of the resultant nanoparticle deposition has been applied in different research and engineering fields. Recent experimental studies have shown that neck-based thermal structure (NTS) by colloidal nanoparticle deposition between microsize filler particle configuration (FPC) can significantly enhance vertical heat conduction in innovative three-dimensional chip stacks [Brunschwiler etal., J. Electron. Packag. 138, 041009 (2016)10.1115/1.4034927]. However, an in-depth understanding of the mechanisms of colloidal liquid drying, neck formation, and their influence on heat conduction is still lacking. In this paper, using the lattice Boltzmann method, we model neck formation in FPCs and evaluate the thermal performances of resultant NTSs. The colloidal liquid is found drying continuously from the periphery of the microstructure to its center with a decreasing drying rate. With drying, more necks of smaller size are formed between adjacent filler particles, while fewer necks of larger size are formed between filler particle and the top/bottom plate of the FPCs. The necks, forming critical throats between the filler particles, are found to improve the heat flux significantly, leading to an overall heat conduction enhancement of 2.4 times. In addition, the neck count, size, and distribution as well as the thermal performance of NTSs are found to be similar for three different FPCs at a constant filler particle volume fraction. Our simulation results on neck formation and thermal performances of NTSs are in good agreement with experimental results. This demonstrates that the current lattice Boltzmann models are accurate in modeling drying of colloidal suspension and heat conduction in microporous structures, and have high potentials to study other problems such as surface coating, salt transport, salt crystallization, and food preserving.

Three influential factors on colloidal nanoparticle deposition for heat conduction enhancement in 3D chip stacks

Thermal management is one of the major challenges facing the development of three-dimensional (3D) chip stacks. Recently, experimental studies have shown that neck-based thermal structure (NTS) between chip layers formed by drying of colloidal suspension in cavity filled with micro-size particles can improve the vertical heat conduction threefold. However, a deep understanding of the mechanisms of neck formation and its influence on heat conduction is still lacking. In this paper, we numerically study the effects of three parameters, i.e., initial nanoparticle concentration, drying temperature and chip surface wettability on neck formation between filler particles and on the resulting heat conduction of the NTS. With increasing nanoparticle concentration, the size and number of necks increase, resulting in an increased effective thermal conductivity (ETC) of NTS. The drying temperature is found to have only little influence on the ETC of resultant NTS, while the neck size and spatial distribution become more uniform at higher drying temperature. When reducing the wettability of the top and bottom surfaces of the cavity, the necks shrink in size until completing evacuating at the top and bottom layers, while the size of the necks between filler particles in the middle height of the cavity expands slowly. In consequence, the ETC of NTS drops at an increasing rate. Being able to reveal the underlying multiple mechanisms of two-phase flow, phase change and heat transport, the current numerical study suggests optimal values for the deposition process, with initial nanoparticle concentration over 0.8%, a drying temperature of 60°C and a uniform contact angle of 30° for practical production of NTS.

Experimental study on boiling performance of wetting fluids in three-dimensional rectangle microchannels

A unique boiling heat transfer study of wetting fluids in a vertical three-dimensional rectangle microchannel was carried out in this paper, to develop a novel passive three-dimensional chip stack cooling technology. The base liquids were deionized water and R113, and Sodium dodecagon sulfate (SDS) was used as a surfactant, which is added into the base fluids for developing wetting fluids. The length, gap, and width of rectangle channels were in the range of 30 mm to 100 mm,30 mm to 50 mm, and 0.4 mm to 4 mm, respectively. Metal wires with different numbers were laid in the rectangle channel along the flow direction for forming change in the width of the microchannel. The study results show that using wetting fluids can significantly enhance both heat transfer coefficients and maximum heat flux of thermosyphon boiling in three-dimensional microchannels compared with that found in pure liquids. The enhanced effects have significant relations with the three-dimensional geometric dimensions. The present experimental results provide significant technology support for passive three-dimensional chip cooling.

(Invited) Heterogeneous Integration Packaging Challenges for Artificial Intelligence

As semiconductor and system scaling has saturated, heterogeneous integration of disparate components in a singular electronic package has become increasingly important. A variety of new packaging techniques are being developed for heterogeneous integration. These techniques include multiple-chip packages incorporating high-density laminated substrates, inter-chip bridges, silicon interposers, and three-dimensional chip stacking. This talk will compare and contrast these varied techniques and identify the associated challenges. These challenges include fine-pitch interconnects, new materials, complex assembly, thermal management, and test and reworkability, among others. Implications to tool development, test protocols, and simulation techniques will also be discussed.

New underfill material based on copper nanoparticles coated with silica for high thermally conductive and electrically insulating epoxy composites

With the microelectronics technology going toward its physical limits and the emergence of three-dimensional chip stack architectures, now more than ever there are both needs and opportunities for novel materials to help address some of these pressing thermal management challenges. In this paper, a high-thermal-conductivity insulative SiO2-coated nano-Cu particle is prepared for new-type underfill materials of high-performance microelectronics packaging. It was found that nano-Cu can be successfully coated with SiO2 by using the surface modification between cetyltrimethyl ammonium bromide and silane coupling agent although nano-Cu particles have silicon-disordered property during the coating process of tetraethyl orthosilicate hydrolysis. Moreover, the thermal conductivity of epoxy mixed with nano-Cu@SiO2 as the packaging underfill is dramatically increased from 0.15 W/m K of the pure-EP and 0.60 W/m K of the EP/SiO2 to 2.9 W/m K due to electronic heat transfer, heat network and fast heat transfer center. It effectively releases the heat generated by the IC device, and the service life of the device is significantly improved from 63 min of pure-EP and 350 min of the EP/nano-SiO2 to 1039 min. The new material creates a challenging environment for keeping modern electronic devices cool, a critical factor in determining their speed, efficiency and reliability.

Study of Three-Dimensional Small Chip Stacking Using Low Cost Wafer-Level Micro-bump/B-Stage Adhesive Film Hybrid Bonding and Via-Last TSVs

Three-dimensional (3-D) small chip stacking using low cost wafer-level insert-bump hybrid bonding and via-last TSVs is proposed and investigated. The proposed hybrid bonding method realized by micro Cu pillar solder bumps and photo-patternable B-stage adhesive film has been successfully applied to an 8 inch wafer with 86 255 gross dies and a bump pitch of 150 μm. The complete process flow is successfully validated and a well electrical connectivity for the whole wafer is obtained. Two hybrid bonding approaches, i.e., “adhesive-first” hybrid bonding and “Cu pillar bump-first” hybrid bonding, are studied. A void-free hybrid bonding interface with a final gap between top chip and bottom chip lower than 30 μm is achieved using the “Cu pillar bump-first” hybrid bonding approach. The interaction of SnAg solder with electroless Ni-P/immersion Au and electro Ni are investigated. Two types of interfacial compounds, i.e., Ni3Sn4 and P-rich Ni layer containing Sn atoms, are found. The via-last through silicon vias (TSVs) have a diameter of 40 μm and a depth of 95 μm. The results indicate that it is a promising method for 3-D integrated circuits stacking technology using hybrid bonding and via-last TSVs.

Enhanced Cu-to-Cu direct bonding by controlling surface physical properties

Cu-to-Cu direct bonding is one of the key technologies for three-dimensional (3D) chip stacking. This research proposes a new concept to enhance Cu-to-Cu direct bonding through the control of surface physical properties. A linear relationship between bonding strength and the value of the bonding face (H: subsurface hardness, R: surface roughness) was found. Low vacuum air plasma and thermal annealing were adopted to adjust the surface physical conditions. Instead of surface activation, an acceleration in copper atom diffusion due to plasma-induced compressive stress accounts for the improvement in bonding strength.

Review on Percolating and Neck-Based Underfills for Three-Dimensional Chip Stacks

Heat dissipation from three-dimensional (3D) chip stacks can cause large thermal gradients due to the accumulation of dissipated heat and thermal interfaces from each integrated die. To reduce the overall thermal resistance and thereby the thermal gradients, this publication will provide an overview of several studies on the formation of sequential thermal underfills that result in percolation and quasi-areal thermal contacts between the filler particles in the composite material. The quasi-areal contacts are formed from nanoparticles self-assembled by capillary bridging, so-called necks. Thermal conductivities of up to 2.5 W/m K and 2.8 W/m K were demonstrated experimentally for the percolating and the neck-based underfills, respectively. This is a substantial improvement with respect to a state-of-the-art capillary thermal underfill (0.7 W/m K). Critical parameters in the formation of sequential thermal underfills will be discussed, such as the material choice and refinement, as well as the characteristics and limitations of the individual process steps. Guidelines are provided on dry versus wet filling of filler particles, the optimal bimodal nanosuspension formulation and matrix material feed, and the over-pressure cure to mitigate voids in the underfill during backfilling. Finally, the sequential filling process is successfully applied on microprocessor demonstrator modules, without any detectable sign of degradation after 1500 thermal cycles, as well as to a two-die chip stack. The morphology and performance of the novel underfills are further discussed, ranging from particle arrangements in the filler particle bed, to cracks formed in the necks. The thermal and mechanical performance is benchmarked with respect to the capillary thermal and mechanical underfills. Finally, the thermal improvements within a chip stack are discussed. An 8 - or 16-die chip stack can dissipate 46% and 65% more power with the optimized neck-based thermal underfill than with a state-of-the-artcapillary thermal underfill.

High Aspect Ratio through Silicon Via Filling By Nickel-Tungsten Alloy Using Graphene As a Conducting and Barrier Layer

Recently, three-dimensional (3D) chip stacking becomes more and more important because of “More than Moore” story. Through silicon via (TSV) technology is one approach to achieve the target of “more than Moore”. However, the coefficient of thermal expansion (CTE) of copper filled in the TSV may lead to failure of the TSV interconnects because the copper CTE is much higher than that of silicon. The packaging materials with different CTEs will induce large stress at interfaces of materials. To overcome this problem, we choose nickel to substitute copper as a filling material of TSV since the nickel CTE is lower than copper CTE. To further decrease the CTE of the filling material, a few tungsten whose CTE is similar to that of silicon is codeposited during filling plating. Graphene has drawn extensive attention due to its outstanding electrical and thermal properties. In addition, graphene can be used as a barrier layer of copper diffusion. Also, the CTE of graphene is similar to that of silicon. Hence, we use graphene to replace the TiN barrier layer and the copper seed layer, which was used in the traditional TSV process. The filling performance is evaluated by examining vertical cross-sections and top-down cross-section of the filled TSVs by using optical microscope (OM). The Ni-W pillar is examined by scanning electron microscopy (SEM). The thermal reliability of the fully filled TSV is evaluated after a thermal annealing process. The CTE of the filled Ni-W is measured by thermomechanical analysis.

Using a Peg with a Small Molecule Weight to Enhance Copper Bottom-up Filling Performance of through Silicon Via with a Deep and Wide Dimensions

Three-dimensional (3D) chip stacking has been proposed for a long time, because “More than Moore” concept has been a possible solution to overcome the limitation of gate line width of a MOS. A deep and wide TSV could be superfilled with copper electroplating within 3 houses, by adding polyethylene glycol (PEG) with a small molecular weight, mainly due to its wetting capability. The dimensions of the TSV used in this work were 50 μm diameter and 245 μm depth. The TSVs used in this work had two types of seed layer. One was a traditional copper seed layer and the other was reduced graphene oxide (rGO) layer. Both TSVs were plated in a copper plating bath containing chloride and acidic copper sulfate as well as a suppressor, leveler and an accelerator. In addition, we added PEG with a small molecular weight. The filled TSVs were examined by cross-sectional analysis using an optical microscope (OM) and a scanning electron microscope (SEM). Keywords Through Silicon Via, Copper Electroplating, Reduced Graphene Oxide, 3D IC References [1] Wei-Ping Dow, Chih-Chan Li, Meng-Wen Lin, Ging-Wen Su, and Chen-Chia Huang “Copper Fill of Microvia Using a Thiol-Modified Cu Seed Layer and Various Levelers” Journal of The Electrochemical Society. 156(8) D314-D320 (2009).[2] Kondo, K, Akolkar, R.N, Barkey, D.P, Yokoi, M "Copper Electrodeposition for Nanofabrication of Electronics Devices, Chapter 2 Supression Effect and Additive Chemistry" Springer, Chemistry, Electrochemistry, Nanostructure Science and Technology (2014). Figure 1

Benchmarking Study on the Thermal Management Landscape for Three-Dimensional Integrated Circuits: From Back-Side to Volumetric Heat Removal

An overview of the thermal management landscape with focus on heat dissipation from three-dimensional (3D) chip stacks is provided in this study. Evolutionary and revolutionary topologies, such as single-side, dual-side, and finally, volumetric heat removal, are benchmarked with respect to a high-performance three-tier chip stack with an aggregate power dissipation of 672 W. The thermal budget of 50 K can be maintained by three topologies, namely: (1) dual-side cooling, implemented by a thermally active interposer, (2) interlayer cooling with four-port fluid delivery and drainage at 100 kPa pressure drop, and (3) a hybrid approach combining interlayer with embedded back-side cooling. Of all the heat-removal concepts, interlayer cooling is the only approach that scales with the number of dies in the chip stack and hence enables extreme 3D integration. However, the required size of the microchannels competes with the requirement of low through-silicon-via (TSV) heights and pitches. A scaling study was performed to derive the TSV pitch that is compatible with cooling channels to dissipate 150 W/cm2 per tier. An active integrated circuit (IC) area of 4 cm2 was considered, which had to be implemented on the varying tier count in the stack. A cuboid form factor of 2 mm × 4 mm × 2.55 mm results from a die count of 50. The resulting microchannels of 2 mm length allow small hydraulic diameters and thus a very high TSV density of 1837 1/mm2. The accumulated heat flux and the volumetric power dissipation are as high as 7.5 kW/cm2 and 29 kW/cm3, respectively.

Modeling Thermal Microspreading Resistance in Via Arrays

As thermal management techniques for three-dimensional (3D) chip stacks and other high-power density electronic packages continue to evolve, interest in the thermal pathways across substrates containing a multitude of conductive vias has increased. To reduce the computational costs and time in the thermal analysis of through-layer via (TXV) structures, much research to date has focused on defining effective anisotropic thermal properties for a pseudohomogeneous medium using isothermal boundary conditions. While such an approach eliminates the need to model heat flow through individual vias, the resulting properties are found to depend on the specific boundary conditions applied to a unit TXV cell. More specifically, effective properties based on isothermal boundary conditions fail to capture the local “microspreading” resistance associated with more realistic heat flux distributions and local hot spots on the surface of these substrates. This work assesses how the thermal microspreading resistance present in arrays of vias in interposers, substrates, and other package components can be properly incorporated into the modeling of these arrays. We present the conditions under which spreading resistance plays a major role in determining the thermal characteristics of a via array and propose methods by which designers can both account for the effects of microspreading resistance and mitigate its contribution to the overall thermal behavior of such substrate–via systems. Finite element modeling (FEM) of TXV unit cells is performed using commercial simulation software (ansys).

An Evolutionary Algorithm for Netlist Partitioning Targeting 3-D FPGAs

Three-dimensional (3-D) chip stacking is considered as the silver bullet technology to preserve Moore’s momentum and fuel the next wave of consumer electronics. However, the benefits of such an integration technology have not yet been explored due to limitations posed mostly by the lack of efficient tools to support application mapping onto these devices. This letter introduces a framework based on a genetic algorithm for netlist partitioning targeting 3-D reconfigurable platforms. Experimental results prove the efficiency of our solution, as we achieve average reduction of the number of utilized through-silicon vias (TSVs) up to 17% for comparable performance metrics against relevant state-of-the-art algorithms.

In-Place Signal and Power Noise Waveform Capturing Within 3-D Chip Stacking

Three-dimensional chip stacking technologies have rapidly progressed in market deployments, calling the strong needs for design and validation techniques of 3-D integrated circuits (ICs). This paper proposes the hybrid of at-speed testing and waveform-based diagnosis for searching the optimum and stable operating conditions of 3-D ICs in an adaptive way to electric properties of a stacked chip structure. A functional silicon interposer features in-place waveform capturing and diagnosis for the quality of signaling and the integrity of power distribution networks (PDNs) deeply within a 3-D chip stack. In-place captured waveforms and eye diagrams are experimentally demonstrated and prove a solid data link operation through vertical TSV channels of 4096-b wide input/output (I/O) bus at the rate of 100 GB/s. While the built-in at-speed self-test functions confirm the bit error rates, the waveform-based diagnosis provides the optimum selection of driving strengths among mini I/O transceivers. The test and diagnosis features therefore play individual roles in validating 3-D IC operations, and exhibit strong correlations in their respective measurements.

Analysis of Thermal Stress and Its Influence on Carrier Mobility in Three-Dimensional Microelectronic Chip Stack

A numerical assessment on the thermal stress in a three-dimensional (3D) microelectronic package structure is performed. The objectives are to study how the chip stack/microbump assembly responds to thermal mismatch induced deformation, and its influences on the electrical performance of devices. The 3D finite element model features a copper through-silicon-via (TSV)/microbump bonding structure connecting two adjacent silicon chips, with and without an underfill layer in between. A case that the entire solder layer has been transformed into an intermetallic layer is also considered. Potential for damage initiation is examined by the measure of stress and strain patterns. It was found that the part of TSV well inside the silicon chip is under high triaxial tensile stresses after thermal cooling, and plastic deformation in copper occurs in and around the microbump regions. The existence of underfill increases plastic strains in the solder joint. The underfill also leads to a significant change in local stress field when the soft solder is transformed entirely into an intermetallic layer. The carrier mobility for the p- and n-type devices is influenced by the stresses in silicon near the TSV; the sizes of “keep-out zone” for the various model configurations are also quantified.

Microvia and through-Hole Filling By Electroplating for Electronic Circuit Fabrication

Electronic products, such as computers, smart phones, laptops and so on, need chips to perform their functions. These chips have many devices, which need to be integrated and connected with each other. To expand the functions of electronic products, more MOS have not met the requirement yet compared with more chips. Therefore, the concept of three-dimensional (3D) chip stacking packaging is proposed. To meet high density interconnection (HDI), through silicon vias (TSVs), through glass vias (TGVs) used as conducting channels of chip stacking need to be fully filled with metal (e.g., copper or nickel-tungsten alloy), and microvia and through hole designed in IC packaging substrates and printed circuit boards (PCBs) need to be fully filled with copper as well. These filling plating technologies have similar process steps but their feature size is totally different.1-11 Herein, we will review these process steps and propose novel filling plating process steps and technologies, including highly selective microvia filling without copper deposition on the outside plane surface, direct through hole filling without usage of a conducting template, TSV filling using CoWP as a barrier layer and electroless copper as a seed layer, TSV filling using reduced graphene oxide (rGO) as barrier and seed layers, TSV filling without copper but rGO combining with NiW alloy, TGV filling using electroless copper as a seed layer and direct pattern copper electroplating onto a glass wafer by using Al-doped ZnO (AZO) as an adhesive and conducting layer.

Fine pitch Cu/Sn solid state diffusion bonding for advanced three-dimensional chip stacking

Three-dimensional (3D) integration requires vertical stacking of dies while forming permanent electrical and mechanical connections between the input/output pins of the devices. How to enable stacking thermal sensitive devices at low temperature gains interest. This paper presents a systematic study of Cu/Sn bonding at 150–200 °C, during which intermetallic compounds were formed by solid state inter-diffusion. It was found that below the lower-limit pressure of 20 MPa it was hard to make good contact between the rough joint surfaces and hence electrical connection was lost. However, beyond the upper-limit of 150 MPa Sn squeezed out leading to electrical shorting between adjacent bumps. Oxides removal was another key factor for good bonding. Finally, this Cu/Sn solid state diffusion bonding together with Cu through-silicon-via (TSV) was used for making die to die vertical interconnection. The measured resistance of single Cu/Sn solder joint and Cu TSV was in the range of 12–25 mΩ.

Optimization of Thermoelectric Coolers for Hotspot Cooling in Three-Dimensional Stacked Chips

Three-dimensional (3D) chip stacking architecture is expected to reduce form factor, improve performance, and decrease power consumption in future microelectronics. High power density and nonuniform power distribution in stacked dies are expected to bring significant thermal challenges for 3D packages due to localized hot spots. Embedded thermoelectric coolers (TECs) have potential to provide reliable and localized cooling at these hot spots. In this work, peak package temperature or active cooling per power consumption of TECs are optimized, considering applied current and thickness of TECs as parameters, for a 3D electronic package with two stacked dies. Each die has two hot spots and one TEC is paired with each hot spot. Three different optimization methods are considered in order to ensure a robust solution. The optimization suggests that both the peak temperature in package and energy efficiency of the cooling system can be significantly improved through the optimization of TECs. TECs are also compared against a configuration where they are replaced by copper blocks or thermal vias. A total of 4.7 °C of additional localized cooling is observed using TECs which is beyond what is achievable with copper vias in place of the TECs. The study also suggests that it is better to use TECs to cool only the hottest portions of the package to avoid introducing additional thermal resistance and Joule heating in the package.

Analysis of 3D TSV Vertical Interconnection Using Pre-applied Nonconductive Films

Much research has been carried out to realize through-silicon via (TSV) technology for three-dimensional (3D) chip stacking packaging. A vertical chip interconnection method using Cu/Sn-Ag bumps and nonconductive films (NCFs) is one of the most promising approaches for 3D TSV vertical interconnection. In this work, the relationship between the viscosity of pre-applied NCFs and loading forces was investigated to predict the gap change between a TSV chip and a substrate chip. Existing theories of squeeze flow are adapted to predict the gap change of a real TSV chip and a substrate chip during TSV bonding using a simplified model. The real gaps measured during bonding of test dies were matched to check the validity of the prediction model. Considering the thixotropy of NCFs, the prediction well matched the real gap changes between bumped TSV chips and substrate chips during bonding.

Through Silicon via Filling by Electroplating Using Reduced Graphene Oxide (rGO) as a Conducting Layer

Graphene materials, including single layer and multi layer graphene platelet, have recently drawn extensive attention due to their outstanding electrical and thermal properties. Reduction of grapheme oxide (GO) is a method for preparing the graphene film. Since GO has a large amount of oxygen functional groups, it can be well dispersed in several solvents and enable it to be coated on a substrate by using a chemical grafting method[1].Three-dimensional (3D) chip stacking is a major focus in recent research and development of microelectronics, MEMS, and MOEMS technology. Through silicon vias (TSVs) play a key role in the 3D IC chip stacking connections. A main advantage of TSV is to make the shortest chip-to-chip vertical interconnection, which allows for size reduction of the chip and reducing signal transmission delay[2]. Electrodeposition plays an important role for TSV metallization, especially copper electrodeposition, which is a critical technology and generally used in the 3D chip packaging.For TSV technology, the thermo-mechanical fatigue may lead to failure in the TSV interconnects[3] because the coefficient of thermal expansion (CTE) of copper is much higher than that of silicon. The package materials with different CTEs will induce large stresses at interfaces. In order to overcome this problem, copper should be substituted by tungsten. However, tungsten cannot be directly plated from an aqueous electrolyte, it can be co-deposited with iron group metals. Alternatively, since the CTE of graphene is much closer to silicon than copper, we choose graphene sheets to substitute copper seed layer.Traditional process for TSV fabrication is a dry process that includes the following step: (1) formation of vias by reactive ion etching; (2) formation of a SiO2isolation layer; (3) deposition of a TiN barrier layer and a copper seed layer; (4) electrodeposition of copper inside the via. In our research, we reduce the procedure of TSV fabrication using a wet process to substitute barrier and seed layer with graphene, and electrodeposition with Ni-W alloy to make a copper-free TSV. In other words, a copper-free TSV with simplified process steps is fabricated, leading to a low fabrication cost. Moreover, a low-stress TSV filled with low CTE materials (Ni-W and rGO) is also fabricated to improve the thermo-mechanical fatigue of TSV, leading to better package reliability.