(Invited) Heterogeneous Integration Packaging Challenges for Artificial Intelligence

Abstract

As semiconductor and system scaling has saturated, heterogeneous integration of disparate components in a singular electronic package has become increasingly important. A variety of new packaging techniques are being developed for heterogeneous integration. These techniques include multiple-chip packages incorporating high-density laminated substrates, inter-chip bridges, silicon interposers, and three-dimensional chip stacking. This talk will compare and contrast these varied techniques and identify the associated challenges. These challenges include fine-pitch interconnects, new materials, complex assembly, thermal management, and test and reworkability, among others. Implications to tool development, test protocols, and simulation techniques will also be discussed.