Thermal characterization and simulation study of 2.5D packages with multi-chip module on through silicon interposer

Abstract

Next generation of heterogeneous integration requires 2.5D package on interposer as enabling technology for less signal delay, faster speed, and more functionality. In this work, thermal characterization and simulation of a 2.5D package with multi chips on through silicon interposer (TSI) are reported. Two dummy chips with chip sizes of 7.6×10.9mm and 8mm×8mm, respectively, are arranged on the interposer through the flip chip bumping and joining process. To facilitate the thermal characterization, a thermal test chip of 5.08×5.08mm is embedded on the same interposer for thermal test and simulation validation. In either molded or bare die BGA package format, the thermal test vehicles are brought for thermal characterization, including Theta JA Theta JB measurement conforming with the JEDEC standards. It is found that the overmolded package has slightly lower thermal resistances than the bare die package. In addition, the Theta JC, namely, the thermal resistance from the junction to the top casing is also characterized through a high performance cold plate. Besides the thermal measurements, thermal simulation models under different boundary conditions are established, respectively, to compare with the thermal measurements. Good agreements are generally achieved between simulation and measurements. Further simulation is also conducted to study the effects of overmold thickness and power dissipation from the multi chips module on the interposer.