Thermal Characterization of Both Bare Die and Overmolded 2.5-D Packages on Through Silicon Interposers

Abstract

The next generation of heterogeneous integration requires 2.5-D packages on through silicon interposer (TSI) as enabling technology for less signal delay, faster speed, and more functionality. In the meantime, the introduction of multiple chips on interposer tends to increase the heat density with added interconnect complexity, which requires systematic thermal analysis and characterization. In this paper, thermal characterization of 2.5-D packages on TSI is reported in both bare-die package and overmolded package formats. The test vehicle consists of two dummy chips and thermal test die assembled on the same interposer of 18 mm × 18 mm × 0.1 mm through the flip chip bumping and joining process. A thermal test chip of 5.08 mm × 5.08 mm is built in with heaters and diodes for thermal characterization. Thermal measurements are conducted for thermal resistances from junction to the ambient, from junction to the board, and from junction to top casing. Measurement accuracy is improved through distributed through silicon via network, multidie temperature monitoring and uncertainty analysis and minimization. It is found that the overmolded package has lower thermal resistances than the bare die package. In addition, the thermal resistance from the junction to the casing is also characterized with a liquid-cooled minichannel cold plate as heat sink, indicating the vast difference between bare die package and molded package. Besides experimental measurements, thermal simulation models under different boundary conditions are established, respectively, to compare with the measurements. Good agreements are generally achieved between simulation and measurements. Further simulation is also conducted to examine the effects of overmold thickness and power dissipation from the multichips module on the interposer.