Wafer process and issue of through electrode in Si wafer using Cu damascene for three dimensional chip stacking

Abstract

The elemental technologies of three-dimensional (3D) LSI chip stacking are described. Chip based stacking technology is under development that includes thorough electrode formation, wafer thinning, chip stacking, and inspection and testing. In order to make over 2,000 bumps on a 10 mm-square chip, the thorough electrode and micro bump dimensions are 10 /spl mu/m square, 20 /spl mu/m pitch. Chips are thinned up to 50 /spl mu/m for high-density packaging. This technology aims to develop the technologies to overcome the performance bottleneck of electronic systems. We summarize the update of this project and discuss wafer process issue.