Electroplating Cu fillings for through-vias for three-dimensional chip stacking

Abstract

Three-dimensional (3D) LSI chip stacking with through chip electrodes can realize high-density packaging and high-speed operation performance because the through chip electrode offers the shortest interconnection between stacked chips. The through chip via size we studied was 10 /spl mu/m-square and 70 /spl mu/m-deep. The void free plating is necessary to avoid problems caused by acid solutions remaining in voids. In this paper, systematic studies of the dependence of electroplating conditions on via filling are described. We found that vias could be almost filled completely.