Abstract
Three-dimensional (3D) chip stacks are receiving more attention for system performance enhancements. However, because of the higher circuit density, the cooling of 3D chip stacks gets more challenging. In conventional cooling methods, a heat sink or a micro-channel cooler is located at the top of the chip to dissipate the generated heat in a chip. In this paper, possible cooling methods from the bottom of a silicon interposer and cooling from the peripheral of a silicon interposer were proposed and evaluated. Based on the experimentally obtained thermal resistance of lead-free (SnAg) interconnections, the cooling performances of the above two cooling solutions were investigated by modeling and the requirements were clarified.
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