Thermal design guideline and new cooling solution for a three-dimensional (3D) chip stack

Abstract

In ASET (Association of Super Advanced Electronics Technologies), the thermal resistances of three-dimensional (3D) chip stacks have been measured by using 3D stacked thermal test chips which are implemented with PN junction diodes for temperature sensors and diffused resistors for heating. The equivalent thermal conductivity of interconnection between stacked chips (SnAg + Cu post) and that of TSV (Through-Silicon-Via) have been derived through these measurements. We propose how to estimate the thermal resistances of various 3D chip stacks, by storing these experimental results. Also, how much heat generation of a 3D chip stack is allowed, is discussed. Further, as one of possible new cooling solutions for a 3D chip stack, cooling though a laminate (organic substrate) is considered, and the thermal resistance dependence of a laminate on the thermal via density is experimentally clarified. It is also investigated how the thermal via material and the resin (dielectric) material affect the laminate thermal resistance by simulation. It is then discussed how much additional heat generation is allowed by this cooling though a laminate.