Thermal resistance evaluation of a three-dimensional (3D) chip stack

Abstract

Three-dimensional (3D) chip stacks are receiving more attention for system performance enhancements, due to their higher interconnect density and shorter interconnect length. However, because of the limited contact area with a cooling method and the higher circuit density, the cooling of 3D chip stacks gets more challenging. In order to determine an appropriate cooling solution for various 3D chip stack cases at the design phase, it is important to estimate the total thermal resistance of a 3D chip stack by correct simulation. In 3D-IC 2009, the thermal resistance of interconnections is experimentally obtained because the interconnections are regarded as one of the thermal resistance bottlenecks of a 3D chip stack. In this study, 3D stacked test chips are fabricated, to determine the thermal effect of interconnections in actual 3D chip stack structure. The temperature distribution of a 3D stacked test chip is measured and the corresponding simulation model is built. The equivalent thermal conductivity of the interconnection layer is obtained to be 1.5 W/mC and it is compared with the measured thermal conductivity of SnAg with Cu posts (37 –41 W/mC).