In-Place Signal and Power Noise Waveform Capturing Within 3-D Chip Stacking

Abstract

Three-dimensional chip stacking technologies have rapidly progressed in market deployments, calling the strong needs for design and validation techniques of 3-D integrated circuits (ICs). This paper proposes the hybrid of at-speed testing and waveform-based diagnosis for searching the optimum and stable operating conditions of 3-D ICs in an adaptive way to electric properties of a stacked chip structure. A functional silicon interposer features in-place waveform capturing and diagnosis for the quality of signaling and the integrity of power distribution networks (PDNs) deeply within a 3-D chip stack. In-place captured waveforms and eye diagrams are experimentally demonstrated and prove a solid data link operation through vertical TSV channels of 4096-b wide input/output (I/O) bus at the rate of 100 GB/s. While the built-in at-speed self-test functions confirm the bit error rates, the waveform-based diagnosis provides the optimum selection of driving strengths among mini I/O transceivers. The test and diagnosis features therefore play individual roles in validating 3-D IC operations, and exhibit strong correlations in their respective measurements.