Third-order Noise Shaping Research Articles

A 13.8-ENOB Fully Dynamic Third-Order Noise-Shaping SAR ADC in a Single-Amplifier EF-CIFF Structure With Hardware-Reusing kT/C Noise Cancellation

To design noise-shaping successive approximation register (NS-SAR) analog-to-digital converters (ADCs) with high resolution and good power efficiency, two key bottlenecks need to be addressed. One is to realize a high-order loop filter with low circuit overhead, and the other is to mitigate the thermal noise. This article presents an NS-SAR ADC that synergistically addresses both challenges. To achieve high-order efficiency, it proposes an innovative error feedback-cascaded integrator feedforward (EF-CIFF) structure that realizes third-order noise shaping using only a single amplifier. It combines the merits of both structures, showing improved robustness, and is free of dc offset concern. On reducing the kT/C noise, this work features a sampling kT/C noise cancellation (SNC) technique that reuses the native hardware of the EF-CIFF structure. An open-loop self-quenching floating-inverter dynamic amplifier (FIDA) is used to support all amplification with low noise and power. Prototyped in 65-nm CMOS, this work achieves 84.8-dB signal-to-noise-distortion ratio (SNDR) with 625-kHz bandwidth (BW) (OSR = 8) and 119 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{W}$ </tex-math></inline-formula> , leading to 182-dB Schreier Figure of Merit (FoM). It uses only 0.8-pF input capacitance, which is <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$5\times $ </tex-math></inline-formula> smaller than prior NS-SAR ADCs with similar oversampling ratio (OSR) and SNDR.

Single low‐gain amplifier compensated hybrid delta‐sigma modulator

This article presents low-power circuit design techniques to achieve third-order noise shaping by employing multiple stages of passive switched-capacitor gain-boosted integrator and a passive switched-capacitor integrator. First integrator is a passive switched-capacitor for higher linearity. Second integrator is a three-stage passive switched-capacitor gain-boosted integrator to provide passive gain to the loop filter as well as the second DAC feedback. While the third integrator is a two-stage passive switched-capacitor gain-boosted integrator to provide passive gain as well as third DAC feedback for higher stability. Multiple lower stages of passive switched-capacitor gain-boosted integrators employed to enhance the noise shaping order of the modulator and suppress the parasitic effect. The preamplifier is the only active block, while the dynamic comparator used as single-bit quantiser. The complete transistor level with thermal noise simulation can achieve 84 dB of dynamic range (DR), 78.2 dB signal-to-noise-plus-distortion ratio (SNDR), and 78.5 dB signal-to-noise ratio (SNR) for 500 Hz signal bandwidth. It can also achieve signal-to-spurious-free dynamic range (SFDR) of 78.2 dB with estimated power consumption of 220 nW at 1 V supply voltage in SMIC 28 nm CMOS Technology. Finally, it can achieve state-of-the-art Walden Figure-of- Merit (FoM W ) of 33 fJ/Conv-Step and Schreier FoM S of 171.2 dB.

160 MS/s 20 MHz bandwidth third‐order noise shaping SAR ADC

This Letter proposes an operational-amplifier free with an embedded passive gain technique to implement an oversampling, noise shaping successive approximation register (SAR) ADCs. In the proposed scheme, the comparator noise, quantisation noise, settling errors and DAC thermal noise are alleviated. A third-order noise shaping SAR ADC with inserted passive gain design in 40 nm CMOS technology is well suited for low power application because of using passive elements like capacitors and switches. Due to the oversampling and shaping scheme, the structure can be used for high-speed and high-resolution operation.

A Mostly Digital VCO-Based CT-SDM With Third-Order Noise Shaping

This paper presents the architectural concept and implementation of a mostly digital voltage-controlled oscillator-analog-to-digital converter (VCO-ADC) with third-order quantization noise shaping. The system is based on the combination of a VCO and a digital counter. It is shown how this combination can function as a continuous-time integrator to form a high-order continuous-time sigma–delta modulator (CT-SDM). The counter consists only of digital building blocks, and the VCOs are implemented using ring oscillators, which are also digital-friendly. No traditional analog blocks, such as opamps, OTAs, or comparators, are used. As a proof of concept, we have implemented a third-order VCO-based CT-SDM for a 10-MHz bandwidth in the low-power version of a 65-nm CMOS technology. This prototype shows a measured performance of 71/66.2/62.5-dB DR/SNR/SNDR at a 10-MHz bandwidth while consuming 1.8 mW from a 1.0-V analog and 1.9 mW from a 1.2-V digital supply. With digital calibration, the nonlinearity could be pushed below the noise level, leading to an improved peak SNDR of 66 dB.

Fully passive third‐order noise shaping SAR ADC

In this Letter, an opamp-free noise shaping successive-approximation register (SAR) ADC is proposed. Third-order noise shaping is achieved by implementing a second-order passive filter and a passive error feedback topology. In the proposed scheme, the SAR error signals (including quantisation noise, comparator thermal noise, DAC thermal noise and settling error) are subjected to third-order noise shaping. Therefore, the thermal noise specifications of the comparator can be relaxed. Also, since no active element is used, the proposed scheme achieves a higher power efficiency than earlier SAR ADCs.

A 12 bit 1 GS/s Dual-Rate Hybrid DAC With an 8 GS/s Unrolled Pipeline Delta-Sigma Modulator Achieving &gt; 75 dB SFDR Over the Nyquist Band

A 12 bit Dual-Rate Hybrid digital-to-analog converter (DAC) architecture with a split Nyquist (1 GS/s) and delta-sigma modulator path (8 GS/s) is proposed and implemented in 65 nm CMOS. Based on the hybrid architecture, the delta-sigma-assisted pre-distortion scheme compensates for the current steering cell mismatch, which further reduces the analog circuit complexity and area. The proposed 8X unrolled pipeline delta-sigma modulator allows for high-speed third-order noise shaping with a digital standard cell design flow. The measured spurious-free dynamic range achieves 91–76 dB over the 500 MHz Nyquist band. The proposed DAC architecture is mostly digital and hence favors future technology scaling.

A Third-Order Low-Distortion Delta-Sigma Modulator with Opamp Sharing and Relaxed Feedback Path Timing

SUMMARY This paper proposes a third-order low-distortion deltasigma modulator (DSM). The third-order noise shaping is achieved by a single opamp (excluding the quantizer). In the proposed DSM structure, the timing limitation on the quantizer and dynamic element matching (DEM) logic in a conventional low-distortion structure can be relaxed from a nonoverlapping interval to half of the clock period. A cyclic analog-to-digital converter with a loading-free technique is utilized as a quantizer, which shares an opamp with the active adder. The signal transfer function (STF) is preserved as unity, which means that the integrators process only the quantization noise component. As a result, the opamp used for the integrators has lower requirements, as low-distortion DSMs, on slew rate, output swing, and power consumption. The proposed third-order DSM with a 4bit cyclic-type quantizer is implemented in a 90-nm CMOS process. Under a sampling rate of 80 MHz and oversampling ratio of 16, simulation results show that an 81.97-dB signal-to-noise and distortion ratio and an 80-dB dynamic range are achieved with 4.17-mW total power consumption. The resulting figure of merit (FOM) is 81.5 fJ/conversion-step.

A 280 mW, 0.07% THD+N class-D audio amplifier using a frequency-domain quantizer

Pulse density modulation (PDM) based class-D amplifiers can reduce non-linearity and tonal content due to carrier signal in pulse width modulation based amplifiers. However, their low-voltage analog implementations also require a linear loop filter and a quantizer. A PDM based class-D audio amplifier using a frequency-domain quantization is presented. The digital intensive frequency-domain approach achieves high linearity under low supply regimes. An analog comparator and a single-bit quantizer are replaced with a current controlled oscillator (ICO) based frequency discriminator. By using the ICO as a phase integrator, a third-order noise shaping is achieved using only two analog integrators. A single-loop, single-bit, class-D audio amplifier is presented with an H-bridge switching power stage, which is designed and fabricated on a 0.18 μm CMOS process with 6 layers of metal achieving a total harmonic distortion plus noise (THD+N) of 0.065% and a peak power efficiency of 80% while driving a 4-Ω loudspeaker load. The amplifier can deliver the output power of 280 mW.

Frequency-to-digital conversion based on sampled phase-locked loop with third-order noise shaping

A new frequency-to-digital architecture based on a phase-locked loop (PLL) is presented, where the voltage controlled oscillator output is sampled before being fed back to one of the phase-frequency detector inputs. A frequency discriminator, located at the PLL sampled output, generates the converter output. Simple analytical models show that the sampling error is shaped by a third-order transfer function just like the quantisation error is shaped in a third-order sigma-delta modulator. The proposed architecture is suitable for integration in modern nanometre CMOS technologies, and it can be used as a FM demodulator.

An 8.1 mW, 82 dB Delta-Sigma ADC With 1.9 MHz BW and $-$98 dB THD

A switched-capacitor low-distortion 15-level delta-sigma ADC is described. It achieves third-order noise shaping with only two integrators by using quantization noise coupling. Realized in a 0.18 mum CMOS technology, it provides 81 dB SNDR, 82 dB dynamic range, and -98 dB THD in a signal bandwidth of 1.9 MHz. It dissipates 8.1 mW with a 1.5 V power supply (analog power 4.4 mW, digital power 3.7 mW). Its figure-of-merit is 0.25 pJ/conversion-step, which is among the best reported for discrete-time delta-sigma ADCs in wideband applications.

A 12-Bit, 10-MHz Bandwidth, Continuous-Time $\Sigma\Delta$ ADC With a 5-Bit, 950-MS/s VCO-Based Quantizer

The use of VCO-based quantization within continuous-time (CT) SigmaDelta analog-to-digital converter (ADC) structures is explored, with a custom prototype in 0.13 mum CMOS showing measured performance of 86/72 dB SNR/SNDR with 10 MHz bandwidth while consuming 40 mW from a 1.2 V supply and occupying an active area of 640 mum times 660 mum. A key element of the ADC structure is a 5-bit VCO-based quantizer clocked at 950 MHz which achieves first-order noise shaping of its quantization noise. The quantizer structure allows the second-order CT SigmaDelta ADC topology to achieve third-order noise shaping, and direct connection of the VCO-based quantizer to the internal DACs of the ADC provides intrinsic dynamic element matching of the DAC elements.

A weak magnetic field measurement system using micro-fluxgate sensors and delta~sigma interface

This paper presents a weak magnetic field measurement system using micro-fluxgate (FG) sensors and a sensor signal processing technique using the delta-sigma modulation in the negative feedback loop. The feedback of the lowpass filtered bitstream output of a delta-sigma modulator to the magnetic field improves system linearity, hysteresis, and stability. In spite of the fact that the second-order delta-sigma modulator is used, the third-order noise shaping can be obtained in the digital output bit-stream by the use of an integrator in the loop. This improves the SNR of the digital output. The measured noise of the implemented system meets the measured noise of the FG sensing element itself. The weak magnetic field in the range of the Earth's magnetic field is successfully measured. The nonlinearity error is less than 0.4% in the range of /spl plusmn/100 /spl mu/T.

High precision D/A converter device for digital audio

A digital-to-analog (D/A) converter device for digital audio that incorporates a new form of noise shaping technology to achieve a theoretical dynamic range of 131 dB was developed. The third-order noise shaping and the D/A converter are presented. Measurement results are given. The device achieved a true accuracy of at least 18 b. >

Multi-stage decimation filter design technique for high-resolution sigma-delta A/D converters

A design technique for a multistage halfband decimation filter structure to enhance the effective resolutions of sigma-delta ( Sigma - Delta ) analog-to-digital (A/D) converters is discussed. In particular, a series of six halfband filters is implemented to obtain more than 18 bits of effective resolution from a digital signal with 12-bit effective resolution. Since this multistage structure is flexible to change the filter design specification, the number of stages in the decimation process can be adjusted to fit the needs for a specific application. By taking advantage of the oversampling methodology and third-order noise shaping by the Sigma -D modulator, more than 120 dB of SNR can be achieved. The theoretical analysis and experimental results with a currently available Sigma - Delta converter are also included. >

Third-order cascaded sigma-delta modulators

A sigma-delta modulator architecture wherein third-order noise shaping is achieved with relatively modest constraints on device matching is explored. The architecture is based on a cascade of a second-order modulator stage followed by a first-order stage, both using 1-b quantization. To improve the dynamic range, the input to the second stage is generated as an asymmetrically weighted error signal from the first stage. An analytical model for assessing the performance and device matching requirements of cascaded architectures is introduced, and computer simulations are used to verify the approximations made in this model. The analytical model is used to show that the proposed architecture offers performance comparable to other third-order cascaded sigma-delta modulator topologies, while being less sensitive to device matching errors. >