Abstract
A 12 bit Dual-Rate Hybrid digital-to-analog converter (DAC) architecture with a split Nyquist (1 GS/s) and delta-sigma modulator path (8 GS/s) is proposed and implemented in 65 nm CMOS. Based on the hybrid architecture, the delta-sigma-assisted pre-distortion scheme compensates for the current steering cell mismatch, which further reduces the analog circuit complexity and area. The proposed 8X unrolled pipeline delta-sigma modulator allows for high-speed third-order noise shaping with a digital standard cell design flow. The measured spurious-free dynamic range achieves 91–76 dB over the 500 MHz Nyquist band. The proposed DAC architecture is mostly digital and hence favors future technology scaling.
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