Thin Silicon Wafers Research Articles

Using silicon disk resonators to measure mechanical losses caused by an electric field.

Several projects of the next generation gravitational-wave detectors use the high purity monocrystalline silicon test masses. The electric field of the actuator that is applied to correct the position of the silicon test mass causes additional mechanical losses and associated noise. Disk mechanical resonators are widely used to study mechanical losses in multilayer optical coatings that are deposited on the test masses of gravitational-wave detectors. We use silicon disk resonators to study losses caused by an electric field. In particular, the dependence of mechanical losses on the resistivity of silicon is investigated. The resonator is a thin commercial silicon wafer in which a low frequency nodal diameter mode is excited. A DC voltage is applied between the wafer and a nearby electrode. We use two measurement configurations. In the first configuration, the dependence of losses on the resistance in the voltage supply circuit is investigated. The dependence of losses on the resistivity of silicon is investigated in the second configuration. We propose a model that relates the electric field induced mechanical loss in disk resonators to the resistivity of the material. Measurements are carried out for low and high resistivity silicon wafers. The measurement results are compared with calculations. Based on these studies, it is possible to estimate the loss and noise of the test masses of gravitational-wave detectors associated with electrostatic actuators.

Study of the mechanical strength of thin silicon wafers in the dependance on their surface treatment during thinning

The mechanical strength of silicon wafers of 100 μm thickness was studied. Loading of the wafers was carried out by the "ring-on ring" method, stress and deflection under the small ring were determined by finite element modeling. The validity of the calculation model was checked by comparing the dependences of the deflection under the small ring on the load obtained in the experiment and by the simulation. The effect of methods of wafers obtaining and their surface treatment on the strength, as well as the connection between the strength and surface roughness characteristics were shown. Keywords: silicon, strength, chemical polishing treatment, surface roughness.

Fracture strength of silicon solar wafers with different surface textures

Surface texturing is widely used in modern photovoltaic converters to improve light capture and increase efficiency. This paper focuses on the influence of the surface texture on the mechanical strength of silicon wafers. Various existing test methods and approaches for measuring the mechanical strength of silicon wafers are discussed and reviewed. The surface morphology of silicon wafers with different textures is characterized by scanning electron microscopy (SEM). The mechanical strength of thin (<200 μm) silicon wafers with different surface textures is measured with a ring-on-ring bending test. A finite element method (FEM) is used to calculate the maximum stress. Weibull statistical theory is applied to the measured fracture stresses. The mean fracture strength, its standard deviation, the Weibull characteristic strength, and the Weibull modulus are obtained for silicon wafers with various surface textures. The fracture strength of silicon wafers is strongly affected by the surface texture. It is found that the fracture strength of silicon wafers with pyramidal textures increases with decreasing size of the pyramids. A new type of surface texture produced by a V2O5 selective oxidation exhibited fracture comparable or higher than that of the wafers with conventional pyramidal textures produced by alkaline etching.

Research on the shape of ground wafer in Back Grinding of Wafer with Outer Rim

Back Grinding of Wafer with Outer Rim (BGWOR) is a new method for carrier-less thinning of silicon wafers. There are few studies on the shape of wafer in BGWOR. In this paper, the mathematical models of three-dimensional grinding marks, surface shape and radial thickness of wafer in BGWOR were developed. With this model, the pattern of grinding marks and the radial thickness of the wafer under different inclination angles of grinding wheel were simulated by Matlab, then the relationship between the angle of grinding wheel shaft and the grinding marks, surface shape, radial thickness, total thickness variation (TTV) of wafer in BGWOR was also discussed. The inclination angles of grinding wheel have great influence on the surface shape and radial thickness distribution of wafer. Finally, the pilot experiments were conducted to verify the theoretical model of radial thickness of wafer in BGWOR. The study results will provide helpful instruction for improving the flatness of ground wafer.

Recent Issues and Configuration Factors in Perovskite-Silicon Tandem Solar Cells towards Large Scaling Production.

The unprecedented development of perovskite-silicon (PSC-Si) tandem solar cells in the last five years has been hindered by several challenges towards industrialization, which require further research. The combination of the low cost of perovskite and legacy silicon solar cells serve as primary drivers for PSC-Si tandem solar cell improvement. For the perovskite top-cell, the utmost concern reported in the literature is perovskite instability. Hence, proposed physical loss mechanisms for intrinsic and extrinsic instability as triggering mechanisms for hysteresis, ion segregation, and trap states, along with the latest proposed mitigation strategies in terms of stability engineering, are discussed. The silicon bottom cell, being a mature technology, is currently facing bottleneck challenges to achieve power conversion efficiencies (PCE) greater than 26.7%, which requires more understanding in the context of light management and passivation technologies. Finally, for large-scale industrialization of the PSC-Si tandem solar cell, the promising silicon wafer thinning, and large-scale film deposition technologies could cause a shift and align with a more affordable and flexible roll-to-roll PSC-Si technology. Therefore, this review aims to provide deliberate guidance on critical fundamental issues and configuration factors in current PSC-Si tandem technologies towards large-scale industrialization. to meet the 2031 PSC-Si Tandem road maps market target.

Obtainment of Residual Stress Distribution from Surface Deformation under Continuity Constraints for Thinned Silicon Wafers

Precision machining (e.g., fine grinding, polishing) induced residual stress is very small and often not constant across the wafer and it is difficult to be directly obtained by stress testing equipment or Stoney equation. The residual stress could be obtained theoretically based on the principle of superposition in which the entire wafer deformation is taken as the sum of all deformations induced by the residual stresses of different positions on the wafer surface. However, the solved residual stress is affected greatly by deformation measurement errors and fluctuates greatly across the wafer surface. To solve the problem, a regularization method with continuity constraints was proposed in this study. The mechanisms for the discontinuity of the residual stress distribution and the sensitivity of calculation results to the measurement errors were studied. The influences of the number of subareas of the silicon wafer were investigated and the continuity constraint term was constructed based on the positional relationship of different subareas. Stable and continuous residual stress distribution was successfully obtained after using the proposed regularization method. The method may also be applied to estimate the residual stress from surface deformation for thin substrate plates of other materials.

Photonic Debonding for Wafer-Level Packaging

Abstract Temporary bonding and debonding (TB/DB) processes have emerged as promising solutions in wafer-level packaging technology. These processes offer a pathway to wafer thinning and subsequent backside processing, which are crucial in enabling heterogenous integration using technologies such as 3D through-silicon-vias (TSVs) and fan-out wafer-level packaging. These are critical for overall device miniaturization and increased performance. In this work, a novel photonic debonding (PDB) method and the corresponding bonding material are presented. PDB enhances the TB/DB process by overcoming many of the disadvantages associated with traditional debonding methods. PDB uses pulsed broadband light (200 nm – 1100 nm) from flashlamps to debond temporarily bonded wafer pairs with glass as the carrier wafer. These flashlamps generate high-intensity pulses of light (up to 45 kW/cm2) over short time intervals (~100 μs) to facilitate the debonding. Feasibility of the PDB in the TB/DB process is demonstrated by successfully debonding thinned (&amp;lt;70 μm) silicon wafers from glass carriers. Post-debond cleaning of the thinned wafers and carriers is evaluated. With uniform, large-area illumination (75 mm x 150 mm) per flashlamp and with the ability to concatenate lamps to increase the illumination area of the PDB tool, the PDB method offers a high-throughput and low-cost debonding solution for both wafer-level and panel-level packaging technologies.

The effect of the chuck shape on the wafer topography in back grinding of wafer with outer rim

Back Grinding of Wafer with Outer Rim (BGWOR) is a novel method for carrier-less thinning of silicon wafers. Silicon wafers are widely used in integrated circuits (ICs). The topography of the wafer will not only directly affect the efficiency of subsequent processing of semiconductor devices, but correspondingly affect the performance and life of these devices. However, there are few studies on the shape of the ground wafer in BGWOR. In this paper, the mathematical model of the wafer topography in BGWOR was developed. With this model, the radial thickness and total thickness variation (TTV) of a wafer under different parameters, including inclination angles and radii of grinding wheel for dressing chuck, were simulated by MATLAB. Inclination angles and radii of grinding wheels for the dressing chuck had a great influence on the radial thickness and TTV of a wafer in the BGWOR. Lastly, the pilot experiments were conducted to validate the theoretical model of grinding topography and TTV of the wafer in BGWOR. To enhance the flatness of the ground wafer, it is essential to control the shape of the dressing chuck. The research results are helpful to the optimization of the dressing process of the chuck in the BGWOR.

Prevention of thinned wafer deformation during thermocompression bonding and multi-die stacking supported by temporary bonding materials

Abstract Process flows for memory stacking or other heterogeneous integration schemes benefit from die bonding on a thinned silicon wafer 100 μm or less. In scenarios where a thinned device wafer contains features such as microbumps or Cu pillars, a carrier and temporary bonding material (TBM) facilitate the support of the fragile landing wafer during thermocompression bonding (TCB). The landing wafer in this case is vulnerable to deformations including loss of die planarity, Si bulging, Si or low k dielectric cracking, and damage to the underlying device wafer topography. In this paper, a dual layer system for temporary bonding is presented that maintains the integrity of a thinned device wafer during and after TCB. This is achieved with TBM materials which do not reflow at typical TCB conditions. The approach is to simulate TCB conditions which demonstrate the performance between different underlying TBM materials. A method which tracks the bond head z-axis over time during a TCB cycle is described which in turn yields information on the degree of temporary substrate deformation due to TCB force and temperature. The experiments include a worst-case scenario of multiple TCB cycles in the same position to mimic multi-die stacking. Finally, the impact of process conditions on Cu pillars with solder caps embedded in a thinned wafer bond line will be discussed.

Evaluation of polishing-induced subsurface damage based on residual stress distribution via measured global surface deformation for thinned silicon wafers

Polishing is widely used to obtain smooth thinned wafer surfaces and the process-induced subsurface damage is often evaluated by scanning electron microscope or transmission electron microscope images. However, the difference of microscope images is very slight and subtle between wafers and affected by the location selection of the measured points. In this study, we explored the method of evaluating the polishing-induced subsurface damage based on residual stress distribution via measured global surface deformation. The surface deformation was first measured and then the polishing-induced residual stress distribution was calculated from the surface topography data by solving the system of linear equations. The polishing-induced subsurface damage could be evaluated independent of the dimension of the silicon wafer by the proposed method. How the thinned silicon wafer was supported during measurement process greatly affected polishing-induced wafer deformation and gravity-induced deformation should be separated from the measured data. Regularization method should be introduced in the calculation of residual stress to reduce the errors caused by the multi-collinearity of the system of linear equations. The calculated residual stress distribution was found to be an obvious centrosymmetric figure and exhibited a quasi-axisymmetric pattern with the axis of symmetry correlated with certain crystalline directions, indicating the effect of anisotropy of monocrystalline silicon in the polishing process. The proposed method could also be used in the evaluation of polishing-induced subsurface damage of other large and thin substrate plates.

Evaluating the Passivation Layer of Freshly Cleaved Silicon Surfaces by Binary Silane‐Based Electrolytes

AbstractThe expansion of silicon anodes in lithium‐ion batteries during lithiation and the resulting instability of its solid‐electrolyte interphase (SEI) has been its Achilles heel for quite some time. Beyond the mechanical damage, this expansion exposes fresh elemental silicon to the electrolyte solution. The electrolyte readily decomposes on the reactive silicon surface. Researchers that test novel electrolytes find it difficult to separate which of the electrolyte components (solvent or anion) decomposes first and diagnose the respective decomposition products. Here, we utilize a straightforward test protocol that reveals which reduces first on bare silicon. We exposed four electrolyte mixtures to elemental silicon in custom made T‐cells by breaking thin silicon wafers in solution. We analyze the resulting surface film layers and compare their composition to the electrolyte's performance in symmetrical lithium cells, and Si/Li cells. We found that unstable anions rather than reactive solvents lead to poor electrochemical performance.

In-Situ Process and Simulation of High-Performance Piezoelectric-on-Silicon Substrate for SAW Sensor

This paper studied the manufacturing process of Piezoelectric-on-Silicon (POS) substrate which integrates 128° Y–X Lithium niobate thin film and silicon wafer using Smart-Cut technology. The blistering and exfoliation processes of the He as-implanted LN crystal under different annealing temperatures are observed by the in-situ method. Unlike the conventional polishing process, the stripping mechanism of the Lithium niobate thin film is changed by controlling annealing temperature, which can improve the surface morphology of the peeling lithium niobate thin film. We prepared the 128° Y–X POS substrate with high single-crystal Lithium niobate thin film and surface roughness of 3.91 nm through Benzocyclobutene bonding. After simulating the surface acoustic wave (SAW) characteristics of the POS substrate, the results demonstrate that the Benzocyclobutene layer not only performs as a bonding layer but also can couple more vibrations into the LN thin film. The electromechanical coupling coefficient of the POS substrate is up to 7.59% in the Rayleigh mode when hLN/λ is 0.3 and hBCB/λ is 0.1. Therefore, as a high-performance substrate material, the POS substrate has proved to be an efficient method to miniaturize and integrate the SAW sensor.

Selective contacts and fill factor limitations in heterojunction solar cells

AbstractCrystalline silicon‐based heterojunction (HJ) solar cells are becoming the best choice for manufacturing companies, because of the low temperature processes useful for very thin silicon wafers and the possibility to easily achieve cells efficiencies higher than 22% on n‐type silicon wafers. However, the maximum cell efficiency is still limited by the typical Fill Factor (FF) value of 82%. This issue is due to several factors, some of which are sometimes underestimated, like the base contact. Indeed, a potential mismatch between the work functions of the transparent conductive oxide and the base doped layer can give rise to a small barrier against electrons collection, which is not easy to recognize when the cell FF overcomes 80%. Also a low doping efficiency of the p‐type amorphous layer at the emitter side can negatively affect the FF. In this case, even if high efficiency cells are produced, their full potential is still unexploited. Thus, both selective contacts of the cell, even if apparently optimized to achieve very good results, can hide problems that limit the final cell FF and efficiency. In a previous work, an experimental method and a model to individuate hidden barriers at the base contact on n‐type crystalline silicon‐based HJs have been provided. In this paper, that model is applied to experimental data obtained from the characterization of both commercial and laboratory level HJ solar cells. Moreover, an easy method to recognize the presence of a barrier to the charge transport at the emitter side of the cell is illustrated.

Training AI-Based Feature Extraction Algorithms, for Micro CT Images, Using Synthesized Data

X-ray computed tomography (CT) is a powerful technique for non-destructive volumetric inspection of objects and is widely used for studying internal structures of a large variety of sample types. The raw data obtained through an X-ray CT practice is a gray-scale 3D array of voxels. This data must undergo a geometric feature extraction process before it can be used for interpretation purposes. Such feature extraction process is conventionally done manually, but with the ever-increasing trend of image data sizes and the interest in identifying more miniature features, automated feature extraction methods are sought. Given the fact that conventional computer-vision-based methods, which attempt to segment images into partitions using techniques such as thresholding, are often only useful for aiding the manual feature extraction process, machine-learning based algorithms are becoming popular to develop fully automated feature extraction processes. Nevertheless, the machine-learning algorithms require a huge pool of labeled data for proper training, which is often unavailable. We propose to address this shortage, through a data synthesis procedure. We will do so by fabricating miniature features, with known geometry, position and orientation on thin silicon wafer layers using a femtosecond laser machining system, followed by stacking these layers to construct a 3D object with internal features, and finally obtaining the X-ray CT image of the resulting 3D object. Given that the exact geometry, position and orientation of the fabricated features are known, the X-ray CT image is inherently labeled and is ready to be used for training the machine learning algorithms for automated feature extraction. Through several examples, we will showcase: (1) the capability of synthesizing features of arbitrary geometries and their corresponding labeled images; and (2) use of the synthesized data for training machine-learning based shape classifiers and features parameter extractors.

Чувствительность отражательных терагерцовых сенсоров водных растворов

Sensitivity of sensors of the composition of aqueous solutions in which it is detected the terahertz pulse reflected from the dielectric film – solution structure is investigated. It is shown that the maximum of the sensitivity is achieved by choosing the angles of incidence and radiation frequencies, providing zero reflection of monochromatic radiation from the named dissipative structure. Conditions for the realization of such reflection for waves of s- and p-polarization are established. Calculations are confirmed experimentally for the sensor of glucose concentration in water, which uses a thin silicon wafer, separating solution from air. It is shown that with the use of the terahertz time-domain spectroscopy method the sensor of the proposed structure allows reliable to detect and distinguich glucose impurities of concentration 10 and 30 g / l.

A Reliable Method for Removing Fabry–Perot Effect in Material Characterization With Terahertz Time-Domain Spectroscopy

Terahertz Time-Domain Spectroscopy (THz-TDS) has been a powerful tool for material characterization. The Fabry–Perot (FP) effect caused by the multiple reflections within the sample exists inherently, which makes the echoes contaminated. In the case of thin samples, different reflection signals may merge together and even the echoes corresponding to the main reflection disappears, making the characterization improper or impossible. To deal with this problem, a novel time-domain optimization method is proposed for removing the FP effect. By introducing a new term which describes the variation of the waveform in time-domain, not only the complex refractive index but also the thickness of material are obtained for a very thin silicon wafer (∼100 μm) whose thickness is less than 2/3 lambda at the central frequency of the THz-TDS system. The accuracy of the algorithm is quite comparable to an iterative method, which is considered to be the most accurate one at the moment, but it is more than 100 times faster, with a better convergence performance. Hence, it is promising for rapid material scenarios such as the in-line quality control and imaging-related applications.

Study into grinding force in back grinding of wafer with outer rim

Back grinding of wafer with outer rim (BGWOR) is a new method for carrier-less thinning of silicon wafers. At present, the effects of process parameters on the grinding force remain debatable. Therefore, a BGWOR normal grinding force model based on grain depth-of-cut was established, and the relationship between grinding parameters (wheel infeed rate, wheel rotational speed, and chuck rotational speed) and normal grinding force was discussed. Further, a series of experiments were performed to verify the BGWOR normal grinding force model. This study proves that the BGWOR normal grinding force is related to the rotational direction of the wheel and chuck, and the effect of grinding mark density on the BGWOR normal grinding force cannot be ignored. Moreover, this study provides methods for reducing the grinding force and optimizing the back thinning process of the silicon wafer.

FPCB Masked One-Step Etching Large Aperture Mirror for LiDAR

This paper presents a Flexible Printed Circuit Board (FPCB) masked one-step etching large aperture mirror for Light Detection and Ranging (LiDAR). A FPCB structure is bonded on a thin silicon wafer ( $50\sim 200~\mu \text{m}$ thick) coated with a 100 nm thick metal film and one-step of DRIE is used to etch the wafer with the FPCB structure as the mask and the metal film as the stop layer. The simple fabrication process and 0.1 mm (instead of $ needed for microfabrication) resolution photolithography lead to a very low cost of a few dollars. Copper coils embedded in the FPCB structure are attached to the backside of the large aperture mirror plate, instead of beside the mirror plate as the case in MEMS magnetic mirrors, to generate a high magnetic force and achieve a relatively high frequency considering the large aperture and high thickness. Modeling and prototyping of two designs, Mirror_A and Mirror_B, are presented to verify the novel mirror technology. LiDAR applications of the novel mirror technology are demonstrated and tested. Achieved performances are: Mirror_A, aperture $12 \times 12$ mm, oscillation frequency of 510 Hz, field of view (FOV) of 30° and radius of curvature (ROC) of 10 m; Mirror_B aperture $24 \times 24$ mm, oscillation frequency of 160 Hz, FOV of 20° and ROC of 10 m. [2020-0085]

Mechanical strength problem of thin silicon wafers (120 and 140 [formula omitted]) cut with thinner diamond wires (Si kerf 120 → 100 [formula omitted]) for photovoltaic use

We compared the mechanical strength of as-sawn thin silicon wafers (120 and 140 μm) cut by thinner diamond wires (Si kerf 120 → 100 μm). The fracture strength was evaluated by applying uniaxial mechanical loads on the fresh- and worn-wire sides of the wafers. The loads were applied parallel and perpendicular to the direction of the wire saw marks. Under parallel loading, wafers from both the fresh- and worn-wire sides had approximately the same low fracture strength, whereas under perpendicular loading, wafers from the fresh-wire side had a larger strength distribution compared to that of wafers from the worn-wire side. Observation by laser microscope revealed deeper pits in the lower strength wafers compared to the higher strength wafers. Observation by ion milling and subsequent scanning electron microscope revealed several cracks below the deeper pits whereas few cracks appeared below the shallower pits. Since the cracks were thought to be the deciding factor in the wafer fracture, we conducted a fractographic study on the fractured surfaces from the perspective of crack propagation. We found that the mechanical strength of the wafers cut by thinner wires showed a larger strength distribution. Although this variation was probably caused by the motion of the thin wire during the sawing process, further study is required for confirmation.

Grinding Marks in Back Grinding of Wafer with Outer Rim

Back Grinding of Wafer with Outer Rim (BGWOR) is a new method for carrier-less thinning of silicon wafers. In this paper, the simulation model of grinding marks of wafer in BGWOR was developed. With the model, the relationship between process parameters, including wheel rotational speed, wafer rotational speed, wheel infeed rate, spark out time and the protruding height of the abrasive grains in the grinding wheel, and grinding marks was discussed. Reasonable grinding parameters to control the grinding marks were also proposed. The model was verified by the experiments of BGWOR. The results showed that: (1) The pattern of the grinding marks of the wafers in BGWOR was depended on the grinding wheel rotational speed, the wafer rotational speed, the wheel infeed rate, the spark out time and the protruding height of the abrasive grains on the grinding wheel; (2) The angle between two adjacent grinding marks changes as the variation of the wheel rotational speed and wafer rotational speed; (3) The grinding marks density can be controlled by selecting the proper ratio of wheel speed to wafer speed. The depth of grinding marks can be reduced by increasing the spark out time and reducing the protruding height of the abrasive grains.