Thin Si3N4 Layer Research Articles

Far-field sub-diffraction focusing and controlled focus shaping of circularly polarized light using a dielectric phase plate

In recent years, sub-diffraction focusing has received substantial attention due to its versatility. However, achieving a flexible sub-diffraction focusing in the far field remains stimulating. Existing techniques either require complex fabrication facilities or are limited to the short focal length and high numerical aperture (NA) of the imaging system. Here, we introduce an optimization method for sub-diffraction focusing of a circularly polarized beam in the far field with a lens of large focal length. A cost-effective dielectric phase plate serves the purpose. By employing a phase plate composed of a thin layer of dielectric Si3N4, the phase of the propagating beam is modulated in the beam’s cross-section, which is divided into two regions of the opposite phase by the plate. A sub-diffraction focusing is achieved for a proper tunning between the two regions. In addition to sub-diffraction focusing, the phase plate is also capable of shaping the focus into a doughnut-shaped and a flat-top profile in the far field. This design provides a simple solution for sub-diffraction focusing and focus shaping that will find potential applications in optical imaging, optical trapping, and material processing.

Ultra-low loss compact active TM mode pass polarizer using phase change material in silicon waveguide

An active low-loss transverse magnetic (TM) pass polarizer, based on the phase change material (Ge2Sb2Te5), is proposed. The proposed polarizer is based on silicon-on-insulator technology that consists of a silicon waveguide that incorporates a thin layer of Si3N4 placed in-between GST. Enhancing the interaction between light and GST is achieved by strategically placing a double-layer GST adjacent to the slot waveguide. The polarizer’s tunability, on the other hand, depends on the shift in the refractive index (RI) of GST as it transitions between its crystalline and amorphous phases. By optimizing the structure, the polarizer exhibits negligible loss for both modes in the amorphous phase, and with the change of phase to crystalline, the loss of TE mode is more than 8 dB. In contrast, the loss of TM is less than 0.05 dB with a high ER of 21.82 dB, propagation length of 79.89 µm and Figure of merit reaches up to 108 at 1550 nm. Due to the combination of these performance parameters, the suggested active TM pass polarizer is an appealing and effective device for various photonic applications. In addition, the fabrication technique of the proposed active TM pass polarizer is explained.

Enhancing AlN PMUTs' Acoustic Responsivity within a MEMS-on-CMOS Process.

In this paper, guidelines for the optimization of piezoelectrical micromachined ultrasound transducers (PMUTs) monolithically integrated over a CMOS technology are developed. Higher acoustic pressure is produced by PMUTs with a thin layer of AlN piezoelectrical material and Si3N4 as a passive layer, as is studied here with finite element modeling (FEM) simulations and experimental characterization. Due to the thin layers used, parameters such as residual stress become relevant as they produce a buckled structure. It has been reported that the buckling of the membrane due to residual stress, in general, reduces the coupling factor and consequently degrades the efficiency of the acoustic pressure production. In this paper, we show that this buckling can be beneficial and that the fabricated PMUTs exhibit enhanced performance depending on the placement of the electrodes. This behavior was demonstrated experimentally and through FEM. The acoustic characterization of the fabricated PMUTs shows the enhancement of the PMUT performance as a transmitter (with 5 kPa V−1 surface pressure for a single PMUT) and as a receiver (12.5 V MPa−1) in comparison with previously reported devices using the same MEMS-on-CMOS technology as well as state-of-the-art devices.

(Invited) Challenges of Graphene Process Integration in CMOS Technology

Compatibility of graphene device fabrication process with Si integrated circuit (IC) manufacturing platforms can enhance the implementation of graphene in electronic and optoelectronic applications and their commercialization. Recent demonstrations of hybrid graphene-Si devices on a wafer scale [1, 2] clearly indicate increasing maturity of the graphene technology. However, there are remaining questions about the manufacturability, as well as the integration and compatibility with Si technology which are seen as prerequisites to the commercialization of graphene (opto-) electronic devices [3, 4]. Despite the remarkable progress in recent years, protocols used for the fabrication of graphene devices often lack the required stability and compatibility which in turn hinders access to the large-scale semiconductor device manufacturing infrastructure. From this point of view, it is of utmost importance to investigate preparation of graphene devices in conditions resembling as close as possible to the Si-based IC production environment. Although this approach may pose inherent risks to the fabrication toolsets, it provides a rare opportunity to explore the engineering aspects of graphene device preparation in a relevant production environment. In this paper we focus on engineering aspects of graphene device fabrication under constraints of manufacturability. We demonstrate some of the key stepping stones which can form a pathway to the fabrication of graphene-based components using tools and processes applied in the IC manufacturing in a 200 mm wafer Si technology environment. As a case study, we present insights into processes of cleaning, patterning, encapsulation, and contacting graphene in a 200 mm wafer pilot line routinely used for the fabrication of ICs in 0.13/0.25um SiGe BiCMOS (bipolar-complementary metal-oxide-semiconductor) technologies. Following the presentation of key process steps and selected electrical characterization results, we point out to the challenges and roadblocks which need to be overcome to enable integration of this material with Si devices. Although Cu substrates offer graphene an outstanding quality, layer transfer from Cu is associated with a significant risk of metallic contaminations which pose limitations on handling of graphene in CMOS processing lines. For this reason, our experiments rely on graphene grown on Ge surfaces which has been proven to be front-end-of-line compatible in terms of purity. Chip-size patches of graphene are transferred from the epi-Ge/Si growth wafer by electrochemical delamination to various sorts of patterned 200 mm wafers on which the further process development takes place. This method of graphene transfer is not yet fully compatible with the Si technology; however, it offers convenient prototyping opportunities as an intermediate solution until full 200mm wafer transfer processes as for example the wafer bonding is developed. Encapsulation of deposited graphene is essential to protect its properties from the environment and the destructive influences of subsequent processing. The key element of the encapsulation in our fabrication scheme is a thin (20 nm-50 nm) SiN layer deposited by low power plasma-enhanced chemical vapor deposition (PECVD). It has been demonstrated that layers of SiN can be grown by PECVD directly on the graphene with excellent uniformity and electrical performance while preserving its crystalline quality and transport properties. The added value of PECVD technique is that it is widely used in the Si IC manufacturing. We adapted this approach to form closed and smooth (rq = 0.47 nm) encapsulating layers of SiN (refractive index n = 2.02 at l = 633 nm) directly on transferred graphene. The second element of the encapsulation is realized by the deposition of a SiO2 layer on the SiN film by using CVD. References Y.-M. Lin, A. Valdes-Garcia, S.-J. Han, D.B. Farmer, I. Meric, Y. Sun, Y. Wu, C. Dimitrakopoulos, A. Grill, P. Avouris, K.A. Jenkins, Science, 332, 1294 (2011)S. Goossens, G. Navickaite, C. Monasterio, S. Gupta, J.J. Piqueras, R. Perez, G. Burwell, I. Nikitskiy, T. Lasanta, T. Galan, E. Puma, A. Centeno, A. Pesquera, A. Zurutuza, G. Konstantatos, F. Koppens, NaturePhotonics, 11, 366 (2017) S. Park, Nature Reviews Materials, 1, 16085 (2016)G. Ruhl, S. Wittmann, M. Koenig, D. Neumaier, Beilstein J. Nanotechnol., 8, 1056 (2017)

Degradation of AlGaN-based metal-semiconductor-metal photodetectors

The degradation of AlGaN-based metal-semiconductor-metal photodetectors under UV illumination has been studied. Oxidation triggered by the presence of moisture and mobile carriers at the semiconductor surface was found to be the degradation mechanism. UVC devices with Al0.5Ga0.5N absorbers show stable performance for more than 1000 h at intensities around 10 mW cm−2 and low dark current when passivated after metallization by SiNx. UVB devices with Al0.25Ga0.75N absorber layers were found to be more sensitive and here additional protection by a thin SiN layer grown in situ in the MOVPE growth chamber against any contamination yielded stable devices. As a result now stable UVB and UVC detectors with high external quantum efficiency, low dark current and no indications for persistent photocurrent are available.

Processing Through Glass Via (TGV) Interposers

For the next generation of 3D-IC applications, glass offers many desirable properties that make it an ideal interposer. In order to realize these applications, it becomes necessary to be able to deposit a Cu layer on both surfaces as well as in the glass via. In this paper we will present results of interposers that have fine line circuitry on both sides of the glass and have through glass vias (TGVs). One major challenge is how to create a TGV using either electrically conductive adhesives (ECAs) or Cu plating methods to achieve a high conductivity and reliable via connection. Most work to date uses ECA materials to fill the TGV, however, many of these ECA materials have limitations in that they cannot withstand temperatures in excess of 400°C, are not hermetic and do not have the electrical properties of bulk Cu. In the first phase of our work, we have evaluated different commercially available ECA materials to fill the glass vias. A major challenge in using these materials is how to effectively fill the vias. Our test vehicle has a TGV with dimensions of 50um diameter and a 300um thickness on 2″ × 2″ glass substrate. A positive pressure screen printing process was used to fill the vias. These ECA materials exhibited a very high viscosity, due to the high Cu metal filler content, which made them very difficult to fill. Different pressures, squeegee speeds, and standoff conditions were evaluated to arrive at an optimized process to effectively fill the glass vias. A tilted X-ray inspection approach was used to characterize the yield for ECA hole fill. A DOE of different sintering conditions was conducted to determine how to maximize the electrically conductivity of the paste. From this work we will show the impact of sintering conditions on electrical conductivity and hermeticity. In parallel, we have developed a process to Cu plate a TGV. In this approach, a dry deposition process was used to produce a conductive seed layer in the via having a diameter of 100um and a total substrate thickness of 300um. We proceeded to use a Cu electroplating process to plate up a conformal Cu layer in the glass via. In this work we have pattern plated circuitry on both surfaces along with the via to produce a glass interposer. In addition, we were able to deposit a very thin layer of Si3N4 between two thick Cu metal layers on the topside of a glass interposer to produce a capacitor. The success of plating a TGV also enables the formation of inductors in a glass substrate. An organic dielectric layer using an Ajinomoto Buildup Film (ABF) was used to create a single buildup layer on the glass interposer. The combination of these individual technologies allows the capability to manufacture a glass interposer for advanced packaging applications. A discussion of the challenges associated in building glass interposers will be presented, which will include examples of recent builds of a double-sided Cu circuitry glass interposer and a diplexer module having Cu MIM (metal-insulator-metal) capacitors and inductors for RF applications.

Selective Epitaxial Growth of III–N Structures Using Ion-Beam Nanolithography

The selective epitaxial growth of GaN by metalorganic vapor-phase epitaxy combined with ion-beam etching is investigated. To this end, partially masked GaN epitaxial layers are fabricated by depositing a thin Si3N4 layer onto the surface in a single technological process with the growth of GaN and the subsequent opening of windows of different shapes in this layer by an ion beam. Selective epitaxial growth regimes are studied. It is shown that, in a situation where the total area of the windows in the mask is small relative to the total area of the sample, the required epitaxy duration should be 5–10 s, which impairs the reproducibility of the parameters of the epitaxial process. It is also shown that the mechanism of the selective growth of submicrometer objects differs significantly from that for planar layers and selectively grown layers with dimensions of ~1 μm or greater. The effect of precursor (trimethylgallium and ammonia) fluxes on the character of selective epitaxy is examined. To investigate the possibilities of varying mask topology for fabricating model objects with regard to photonic crystals, the impact of the shape and orientation of the windows in the Si3N4 mask on the character of selective epitaxy is studied.

3D-fabrication of tunable and high-density arrays of crystalline silicon nanostructures

In this report, a procedure for the 3D-nanofabrication of ordered, high-density arrays of crystalline silicon nanostructures is described. Two nanolithography methods were utilized for the fabrication of the nanostructure array, viz. displacement Talbot lithography (DTL) and edge lithography (EL). DTL is employed to perform two (orthogonal) resist-patterning steps to pattern a thin Si3N4 layer. The resulting patterned double layer serves as an etch mask for all further etching steps for the fabrication of ordered arrays of silicon nanostructures. The arrays are made by means of anisotropic wet etching of silicon in combination with an isotropic retraction etch step of the etch mask, i.e. EL. The procedure enables fabrication of nanostructures with dimensions below 15 nm and a potential density of 1010 crystals cm−2.

Arrayed waveguide grating spectrometers for astronomical applications: new results.

One promising application of photonics to astronomical instrumentation is the miniaturization of near-infrared (NIR) spectrometers for large ground- and space-based astronomical telescopes. Here we present new results from our effort to fabricate arrayed waveguide grating (AWG) spectrometers for astronomical applications entirely in-house. Our latest devices have a peak overall of ∼23%, a spectral resolving power (λ/δλ) of ~1300, and cover the entire H band (1450-1650 nm) for Transverse Electric (TE) polarization. These AWGs use a silica-on-silicon platform with a very thin layer of Si3N4 as the core of the waveguides. They have a free spectral range of ~10 nm at a of ~1600 about wavelength nm and a contrast ratio or crosstalk of 2% (-17 dB). Various practical aspects of implementing AWGs as astronomical spectrographs are discussed, including the coupling of the light between the fibers and AWGs, high-temperature annealing to improve the throughput of the devices at ~1500 nm, cleaving at the output focal plane of the AWG to provide continuous wavelength coverage, and a novel algorithm to make the devices polarization insensitive over a broad band. These milestones will guide the development of the next generation of AWGs with wider free spectral range and higher resolving power and throughput.

Through‐layer XPS investigations of the Si3N4/AlGaN interface

Investigations of chemical species at the dielectric/III‐N interface remain an important question in order to understand the chemical origin of the surface states, which are present at the heterostructure surface. In this work, we demonstrate a sample preparation technique to analyze the existing interface species by X‐ray photoelectron spectroscopy (XPS) through thin uniform silicon nitride (Si3N4) layers 1.4 ± 0.2 nm. We show that it is crucial that the layers are as thin as possible but as thick as necessary to avoid oxygen diffusion through the passivation. Due to the sufficient information depth provided by such layers, the photoelectrons are detected. This is an advantage over sputtering as no intermixing of atoms or cleavage of bonds occurs. We show that the deposited Si3N4 hinders oxygen diffusion through the layer to the AlGaN surface. Selective SiO2 over Si3N4 etching and XPS depth profiles indicate that ∼1 nm of the thin Si3N4 layer has formed a surface oxide. Angle‐resolved XPS measurements confirm the accumulation of oxygen at the top and bottom Si3N4 interfaces. No indication is found that interfacial oxygen is bound to any other than the group‐13 metal. In agreement with the HSAB concept, the interfacial oxygen is bound to Al rather than Ga.Scheme of the nondestructive XPS interface analysis of the dielectric/AlGaN interface.

Fiber-chip edge coupler with large mode size for silicon photonic wire waveguides.

Fiber-chip edge couplers are extensively used in integrated optics for coupling of light between planar waveguide circuits and optical fibers. In this work, we report on a new fiber-chip edge coupler concept with large mode size for silicon photonic wire waveguides. The coupler allows direct coupling with conventional cleaved optical fibers with large mode size while circumventing the need for lensed fibers. The coupler is designed for 220 nm silicon-on-insulator (SOI) platform. It exhibits an overall coupling efficiency exceeding 90%, as independently confirmed by 3D Finite-Difference Time-Domain (FDTD) and fully vectorial 3D Eigenmode Expansion (EME) calculations. We present two specific coupler designs, namely for a high numerical aperture single mode optical fiber with 6 µm mode field diameter (MFD) and a standard SMF-28 fiber with 10.4 µm MFD. An important advantage of our coupler concept is the ability to expand the mode at the chip edge without leading to high substrate leakage losses through buried oxide (BOX), which in our design is set to 3 µm. This remarkable feature is achieved by implementing in the SiO2 upper cladding thin high-index Si3N4 layers. The Si3N4 layers increase the effective refractive index of the upper cladding near the facet. The index is controlled along the taper by subwavelength refractive index engineering to facilitate adiabatic mode transformation to the silicon wire waveguide while the Si-wire waveguide is inversely tapered along the coupler. The mode overlap optimization at the chip facet is carried out with a full vectorial mode solver. The mode transformation along the coupler is studied using 3D-FDTD simulations and with fully-vectorial 3D-EME calculations. The couplers are optimized for operating with transverse electric (TE) polarization and the operating wavelength is centered at 1.55 µm.

Design and Characterization of a Sensorized Microfluidic Cell-Culture System with Electro-Thermal Micro-Pumps and Sensors for Cell Adhesion, Oxygen, and pH on a Glass Chip.

We combined a multi-sensor glass-chip with a microfluidic channel grid for the characterization of cellular behavior. The grid was imprinted in poly-dimethyl-siloxane. Mouse-embryonal/fetal calvaria fibroblasts (MC3T3-E1) were used as a model system. Thin-film platinum (Pt) sensors for respiration (amperometric oxygen electrode), acidification (potentiometric pH electrodes) and cell adhesion (interdigitated-electrodes structures, IDES) allowed us to monitor cell-physiological parameters as well as the cell-spreading behavior. Two on-chip electro-thermal micro-pumps (ETμPs) permitted the induction of medium flow in the system, e.g., for medium mixing and drug delivery. The glass-wafer technology ensured the microscopic observability of the on-chip cell culture. Connecting Pt structures were passivated by a 1.2 μm layer of silicon nitride (Si3N4). Thin Si3N4 layers (20 nm or 60 nm) were used as the sensitive material of the pH electrodes. These electrodes showed a linear behavior in the pH range from 4 to 9, with a sensitivity of up to 39 mV per pH step. The oxygen sensors were circular Pt electrodes with a sensor area of 78.5 μm2. Their sensitivity was 100 pA per 1% oxygen increase in the range from 0% to 21% oxygen (air saturated). Two different IDES geometries with 30- and 50-μm finger spacings showed comparable sensitivities in detecting the proliferation rate of MC3T3 cells. These cells were cultured for 11 days in vitro to test the biocompatibility, microfluidics and electric sensors of our system under standard laboratory conditions.

A polymer-based surface grating coupler with an embedded Si3N4 layer

Polymer has been considered to be an ideal material option for integrated photonics devices. To measure these devices, normally the route of edge coupling is chosen to couple the light into or out of the polymer waveguide, which, however, demands a more difficult alignment procedure compared to the surface coupling. Due to the relatively low refractive indices of polymers, implementing the surface grating coupler for surface coupling in this material system remains a challenge. In this paper, we present a polymer-based surface grating coupler. Rather than through expensive complementary metal–oxide–semiconductor (CMOS) fabrication, the device is fabricated through a simple and fast UV-based soft imprint technique utilizing self-developed low-loss polymer material. The coupling efficiency is enhanced by embedding a thin Si3N4 layer between the waveguide core and under cladding layer. Around −19.8 dB insertion loss from single-mode fiber (SMF) to single-mode fiber is obtained for a straight waveguide with a grating coupler at each end. If the output light is collected with a multimode fiber, the insertion loss can be reduced to around −17.3 dB. Near 12% of the coupling efficiency is achieved between the polymer waveguide and SMF. The 3 dB bandwidth of the transmission is 32 nm and is centered at 1550 nm. The proposed surface grating coupler and its easy fabrication method would be very attractive for practical applications.

Formation of V-grooves on the (Al,Ga)N surface as means of tensile stress relaxation

In this paper we present a study of the relaxation mechanism of the top Al0.30Ga0.70N layer grown on GaN, as used in High Electron Mobility Transistor (HEMT) structures. We show that the initial mechanism for relaxation of strain is by means of formation of V-grooves on the surface of the Al0.30Ga0.70N. It is also demonstrated that a thin Si3N4 layer, grown in-situ, immediately after the AlxGa1−xN can “freeze-in” the surface structure. Using tapping mode Atomic Force Microscopy (AFM) it can be observed that immediately after termination of the growth of the thin Al0.30Ga0.70N layer, the steps on the surface show round shape and spiral-like features. After about 1 min of annealing time under NH3 flow the surface structures become straighter. Upon prolonged annealing a V-groove pattern is observed. These V-grooves run along the 〈−1–120〉 directions.Although some other facets can be observed, from cross-sectional Transmission Electron Microscopy (TEM) images we can infer that the side walls of the grooves are {1–101} planes and that the grooves do not penetrate till the Al0.30Ga0.70N/GaN interface. Therefore, we come to the conclusion that the initial relaxation of a thin Al0.30Ga0.70N layer does not occur via a dislocation glide mechanism leading to the formation of an array of misfit dislocations at the Al0.30Gas.70N/GaN interface. Instead, we propose that the mechanism is by surface instability leading to V-groove formation.

Optical Gratings Coated with Thin Si3N4 Layer for Efficient Immunosensing by Optical Waveguide Lightmode Spectroscopy.

New silicon nitride coated optical gratings were tested by means of Optical Waveguide Lightmode Spectroscopy (OWLS). A thin layer of 10 nm of transparent silicon nitride was deposited on commercial optical gratings by means of sputtering. The quality of the layer was tested by x-ray photoelectron spectroscopy and atomic force microscopy. As a proof of concept, the sensors were successfully tested with OWLS by monitoring the concentration dependence on the detection of an antibody-protein pair. The potential of the Si3N4 as functional layer in a real-time biosensor opens new ways for the integration of optical waveguides with microelectronics.

Fusion bonding of silicon nitride surfaces

While silicon nitride surfaces are widely used in many micro electrical mechanical system devices, e.g. for chemical passivation, electrical isolation or environmental protection, studies on fusion bonding of two silicon nitride surfaces (Si3N4–Si3N4 bonding) are very few and highly application specific. Often fusion bonding of silicon nitride surfaces to silicon or silicon dioxide to silicon surfaces is preferred, though Si3N4–Si3N4 bonding is indeed possible and practical for many devices as will be shown in this paper. We present an overview of existing knowledge on Si3N4–Si3N4 bonding and new results on bonding of thin and thick Si3N4 layers. The new results include high temperature bonding without any pretreatment, along with improved bonding ability achieved by thermal oxidation and chemical pretreatment. The bonded wafers include both unprocessed and processed wafers with a total silicon nitride thickness of up to 440 nm. Measurements of bonding strength, void characterization, oxidation rate and surface roughness are also presented. Bonding strengths for stoichiometric low pressure chemical vapor deposition Si3N4–Si3N4 direct fusion bonding in excess of 2 J cm−2 are found. The stoichiometry is verified indirectly through refractive index and intrinsic stress measurements. The importance of surface oxide in Si3N4–Si3N4 fusion bonding is investigated by x-ray photoelectron spectroscopy measurements.

Kelvin probe force gradient microscopy of charge dissipation in nano thin dielectric layers

Application of Kelvin probe force gradient microscopy (KPFGM) to visualize the local charge dissipation in thin dielectric layers is considered. By this method, the local charge behavior in nano thin SiO2, Si3N4, and LaScO3 dielectric layers has been studied. Local charging of the layers has been performed at the point contact with a conductive probe. KPFGM potential images reveal variations of the surface potential in the locally charged areas, which makes it possible to detect the injected charge and to study its behavior. Special experiments on the SiO2 layers with embedded Si-nanocrystals, when lateral spreading of injected charge had been suppressed, permitted to demonstrate high (better than 20 nm) lateral resolution of KPFGM observations. A simple electrostatic model has been developed to estimate the total amount of injected charge. The obtained estimations made it possible to control charge retention in the dielectric layer and possible leaks into the substrate. The studied dielectric layers demonstrate a broadening of the charged area with time t, proportionally to t1/2, what indicates the domination of the diffusion mechanism in charge lateral spreading on the large time scale. These observations permitted to determine the diffusion coefficients, mobilities, and diffusion activation energies for charges in the studied dielectric layers. To obtain the correct information on the injected charge behavior, the parasitic charge dissipation through the surface film of adsorbed water should be reduced to a negligible level. It was achieved by working in moderate vacuum conditions with an additional sample heating.

Bundled Silicon Nitride Nanorings

Bundled nanorings composed of several self-coiled nanowires are synthesized by catalyst-assisted pyrolysis of a polymeric precursor. Microstructural observation reveals that the nanowires have a bilayer structure consisting of a thin single-crystal Si3N4 layer and a thick amorphous layer. The thickness ratio of the two layers is ∼ 1:2, regardless of the nanowire size. The formation of the thick amorphous layer is likely due to the high Al concentration within the precursor. The self-coiling mechanism is discussed and attributed to the difference in growth rates of the two layers. A phenomena model is proposed to account for the formation of the nanoring structure.

Interdiffusion, phase formation, and stress development in Cu–Pd thin-film diffusion couples: Interface thermodynamics and mechanisms

Cu–Pd thin-film diffusion couples (individual layer thicknesses of 50nm) have been prepared by dc-magnetron sputtering on silicon substrates coated with a thin amorphous Si3N4 layer. Stress evolution, microstructural development, and phase formation during interdiffusion have been investigated employing Auger-electron spectroscopy (in combination with sputter-depth profiling), x-ray diffraction, wafer curvature measurements and transmission electron microscopy. Upon annealing at relatively low temperatures (175–250°C) for durations up to 10h, considerable diffusional intermixing occurs. Interdiffusion is accompanied by sequential formation of new phases. First, Cu3Pd forms; subsequently, CuPd forms and grows at the expense of Cu3Pd, which has been interpreted as a consequence of interface thermodynamics. Annealing leads to a slight sharpening of the pre-existing {111}-fiber textures and a little increase in the average grain size. A combination of ex situ (x-ray diffraction) and in situ (wafer curvature) stress measurements revealed that tensile stresses are generated during annealing. The obtained stress results have been discussed in the light of possible mechanisms of stress generation, and the dominant sources of stress buildup and relaxation have been identified.

Fabrication and test of multilayer microcoils with a high packaging density

In magnetic microactuation, the energy converted by a magnetic microactuator is proportional to its volume (Kohlmeier et al., Microsystem Technol 8(4–5):304–307, 2002a). For that reason, it is desirable not only to choose an actuator’s active part with a sufficient footprint size, but also with a substantial building height. By applying UV depth lithography, such a requirement may be fulfilled. This paper investigates the application of high aspect ratio systems technology to fabricating a compact microcoil as field generating element. The coil has four layers. To take optimal advantage of the building height, the insulation film between the coil layers was kept small by applying a thin Si3N4 layer. The coils are intended for the integration in a magnetic microlevitation system serving as an electromagnetic guide for a linear microhybrid step motor (Budde et al., In: Proceedings of the 9th int. conf. on new actuators, pp 665–668, 2004).