Thin SiGe Research Articles

GIDL Characteristics in Gated-Diode Memory String and Its Application to Current-Steering Digital-to-Analog Conversion

This paper investigates gate-induced drain leakage (GIDL) characteristics in a cell string consisting of gated-diode memory cells. Gated-diode cells have an oxide/ nitride/oxide gate dielectric stack to implement a nonvolatile memory and are formed in a cell string with a select MOSFET located at one end. Gated diodes in a string are investigated with regard to memory performance. The string current is the sum of individual GIDL currents from the cells. It can be accurately controlled by programming or erasing the cells. Using a $1\times 6$ cell string, a 6-b binary-weighted current-steering digital-to-analog converter (DAC) is demonstrated experimentally. By programming the cells to have binary-weighted cell currents by means of an incremental step pulse programming, the effective number of bits becomes 5.98 b in the DAC. As a means of increasing the GIDL current, a thin SiGe epilayer is adopted, with a simulated current improvement of more than $10^{3}$ times at a gate voltage of −3 V.

2D strain measurement in sub-10 nm SiGe layer with dark-field electron holography

In this paper, we carried out the two-dimensional (2D) strain measurement in sub-10 nm SiGe layer; images were obtained by dark-field electron holography (DFEH). This technique is based on transmission electron microscopy (TEM), in which dark-field holograms were obtained from a (400) diffraction spot. The measured results were compared to the X-ray diffraction (XRD) results in terms of the strain value and the depth of strain distribution in a very thin SiGe layer. Subsequently, we were able to successfully analyze the 2D strain maps along the [100] growth direction of the nanoscale SiGe region. The strain was measured and found to be in the range of 1.8–2.4%. The strain precision was estimated at 2.5 × 10−3. As a result, the DFEH technique is truly useful for measuring 2D strain maps in very thin SiGe layers with nanometer resolution and high precision.

Strain/composition interplay in thin SiGe layers on insulator processed by Ge condensation

We study the interplay between strain and composition during the elementary process steps which allow the fabrication of strained ultra-thin SiGe layers on insulators from a Silicon-On-Insulator (SOI) substrate by the Ge condensation technique. Strain maps with subnanometer resolution and high precision are obtained using the dark-field electron holography technique. We confirm that two basic mechanisms drive the final composition of the top layer, namely Ge injection during oxidation and Si/Ge interdiffusion, both thermally activated. We show that during this process the observed strain results from the out-of-plane relaxation of the stress generated by the substitution of Si by Ge atoms in the Si lattice, rigidly bounded to the underlying buried oxide.

(Invited) Strained-SiGe Channel FinFETs for High-Performance CMOS: Opportunities and Challenges

The effectiveness of widely-used CMOS stressors, such as compressive stress liners and embedded source/drain is significantly decreased in the state-of-the-art CMOS as the gate pitch is scaled down and device architecture is transformed from planar to 3D non-planar architectures, such as FinFETs. The issue is more pronounced for FinFETs fabricated on the SOI substrates. It is well known that SiGe is a great candidate for p-type MOSFETs due to its intrinsic lower effective mass and better transport properties than Si and has been utilized in CMOS industry for IBM SOI 32nm and 22nm generations, as a key knob to adjust the PFET threshold voltage and performance enhancement [1, 2]. However, it is shown that SiGe with moderate Ge content and no strain does not provide noticeable transport (neither long-channel nor short-channel) benefit over Si and it is believed that the strain plays a significant role in high-performance (HP) SiGe channel pFETs [3]. The strain state in typical thin SiGe substrates grown on bulk Si or SOI is biaxial compression. It has been shown that by patterning of biaxially strained SiGe layers, strain can be transformed to asymmetric strain (uniaxial for FinFET) where the effective mass is significantly lowered and higher hole velocities can be achieved. Hole transport can be significantly improved by increasing the Ge content as well as the built-in strain, while the second component (strain) has a stronger impact on the transport enhancement. However, higher-Ge content SiGe offers reduced bandgap and may result in increased gate-induced –drain-leakage (GIDL) and high off current due to increased band-to-band or trap-assisted tunneling. This brings concern for some CMOS applications, such as I/O devices and SRAM. Moreover, the interface passivation for higher Ge content SiGe is extremely challenging and can cause significant sub-threshold leakage and degraded low field mobility. The direct consequence is the degraded short-channel on-state current at the target off-current at a scaled power-supply voltage, VDD. In order to experimentally investigate the device characteristics of SiGe FinFETs, we have fabricated strained-Si1-xGex-on-insulator pMOS FinFETs with Ge fraction, x~0.3-0.5 using CMOS-compatible process flows which allow us co-integration with Si or strained-Si for n-type transistors. Highly-compressively-strained SGOI substrates were fabricated using Ge condensation processes and strain transformation to uniaxial was verified by Raman spectroscopy. A gate-first high-K/metal-gate flow with ion-implant-free raised-S/D and aggressively scaled fin and spacer dimensions has been developed to fabricate devices with aggressively scaled gate lengths [4]. A Si-cap-free scheme was developed for the interface passivation to allow CET scaling and eliminate the epitaxial related issues on the 3D architectures. We have observed that non-optimized passivation may result in relatively high interface trap densities and sub-threshold slopes (SS) around 75-80mV/dec for x~0.3 and over 80mV/dec for x~0.5. However, by optimizing the passivation process using a Si-cap-free approach, impressive SS=65mV/dec and 68mV/dec has been achieved for SGOI FinFETs with x~0.3 and x~0.5, respectively. Moreover, significant transport benefit in terms of mobility and drive current has been achieved due to the improved passivation [5]. As a result, we have reported superior mobility characteristic for SGOI pMOS FinFETs with x~0.5 over the state of the art Si, SiGe or relaxed-Ge FinFETs [6]. We have also investigated the short-channel GIDL characteristics of surface-channel strained-Si1-xGex pMOS FinFETs. We have shown devices having a minimum GIDL current of 1nA/μm for x~0.3 and 20nA/μm for x~0.5 at an operating voltage of VDD=0.8V and an operating temperature of 50°C. Temperature-dependent leakage current measurements demonstrate that the GIDL caused by band-to-band tunneling is the dominant leakage mechanism as compared to trap-assisted tunneling for both cases [7]. In summary, we have reported process integration and electrical characterization of SGOI FinFETs with aggressively scaled gate and fin dimensions and Ge content x~0.3-0.5 using an improved Si-cap-free surface passivation process. SiGe-OI FinFETs with x~0.3 can offer superior pMOS characteristics and are promising candidate for both high-performance and low-power applications. On the other hand, while SiGe-OI FinFETs with x~0.5 can offer extremely high mobility and high current drive and transconductance which is applicable to high-performance CMOS, their operation even at low VDD could be a concern for low-power applications, similar to the state-of-the-art Ge FinFETs [8]. S. Krishnan et al., IEEE IEDM, 634 (2011).C. Ortolland et al., IEEE IEDM, 236 (2013).A. Khakifirooz et al., IEEE EDL, 34, 1358 (2013).P. Hashemi et al., Symp. VLSI Tech., 18 (2013).P. Hashemi et al., Symp. VLSI Tech., 18 (2014).P. Hashemi et al., IEEE IEDM, 16.1 (2014).K. Balakrishnan et al., IEEE DRC, 183 (2014).B. Duriez et al., IEEE IEDM, 522 (2013).

Deposition of thin Si and Ge films by ballistic hot electron reduction in a solution-dripping mode and its application to the growth of thin SiGe films

To enhance the usefulness of ballistic hot electron injection into solutions for depositing thin group-IV films, a dripping scheme is proposed. A very small amount of SiCl4 or GeCl4 solution was dripped onto the surface of a nanocrystalline Si (nc-Si) electron emitter, and then the emitter is driven without using any counter electrodes. It is shown that thin Si and Ge films are deposited onto the emitting surface. Spectroscopic surface and compositional analyses showed no extrinsic carbon contaminations in deposited thin films, in contrast to the results of a previous study using the dipping scheme. The availability of this technique for depositing thin SiGe films is also demonstrated using a mixture SiCl4+GeCl4 solution. Ballistic hot electrons injected into solutions with appropriate kinetic energies promote preferential reduction of target ions with no by-products leading to nuclei formation for the thin film growth. Specific advantageous features of this clean, room-temperature, and power-effective process is discussed in comparison with the conventional dry and wet processes.

Structure and optical properties of Si and SiGe layers grown on SiO2 by chemical vapor deposition

The properties of thin Si and SiGe layers grown on SiO2 by chemical vapor deposition (CVD) were studied using transmission electron and atomic force microscopies, and Raman and photoluminescence (PL) spectroscopies. The layers with a composition of Si0.5Ge0.5 become composed of nanocrystals with an average size of about 100nm at growth temperatures of 550°C which is significantly lower than that for the pure Si layers. Moreover, the Si0.5Ge0.5 layers exhibit a broad PL peak centered at 0.8eV, whereas the bandgap of unstrained Si0.5Ge0.5 is about 1eV. This indicates that PL occurs through deep energy levels in the bandgap, which can be associated with crystal defects. The predominance of deep-level PL in radiative emission can be the result of a high concentration of defects that appear due to a low growth temperature.

SiGe channel deposition by batch epitaxy

Batch epitaxy has been introduced for high volume manufacturing of SiGe channels in order to reduce the cost for this epitaxial process by a factor of 3. Beside cost, SiGe channel deposition by batch epitaxy offers many benefits for manufacturing. The stability of the process and the reduced variability of the SiGe thickness greatly improve the variation of VT. The batch epitaxy process does not show a pattern loading effect for SiGe thickness reducing the complexity for manufacturing significantly. However, since the tool concept is very different to that of the widely used single wafer tools, there are some tool specific issues that need to be managed. The wafer backside is critical for batch epitaxy. A nitride backside facing the front side of the wafer results in a clear degradation of the uniformity and a change of the morphology of the SiGe channel compared to that facing a Si backside. The thermal rounding is more pronounced for the channels deposited in a batch tool for both large and narrow width devices. The device parameters of the large width device are not affected by thermal rounding but the performance of the narrow width device is clearly degraded. The thin SiGe layer at the edge of the channel driven by thermal rounding affects the VT and thus the effective device width. An in-situ etching before SiGe deposition to avoid thermal rounding was not feasible due to defects issues which were induced by the wafer backside. Finally a thermal rounding of the Si by an aggressive H2 bake before SiGe deposition improves the SiGe channel uniformity and recovers the performance degradation of the narrow width device partly.

Micro‐Raman spectroscopy as a complementary technique to high resolution X‐ray diffraction for the characterization of Si1‐xGex thin layers

AbstractIn advanced transistor technology, Silicon‐Germanium alloy (SiGe) is being used as a replacement for Si channels to achieve higher mobility. Among the various characterization techniques μ‐Raman spectroscopy is a promising candidate due to a good spatial resolution and low detection threshold. This study presents the evaluation of the technique for the measurement of Ge concentration and comparison to other metrology techniques. As a first step to evaluate the μ‐Raman capability, we considered a simple case of thin SiGe films from 12nm down to 4 nm thickness. Assuming an epitaxial pseudomorphic structure, the Ge content has been extracted for all samples with an average 0.3% stability and at least 1% accuracy as confirmed by high resolution X‐ray diffraction (HRXRD) and secondary ion mass spectrometry analysis (SIMS). We then studied a more complex structure of SiGe on fully depleted‐silicon on insulator (FD‐SOI) as being critical for the development of condensation process of advanced transistor technology. Since μ‐Raman requires prior knowledge of the structural state of the layer, we discuss the interest to combine μ‐Raman measurements with X‐rays diffraction in order to extract the Ge composition on such stacks. μ‐Raman shows a real potential for thin SiGe film characterization and it does not suffers of the lack of precision for very thin films as HRXRD does, however there are still some developments to be made before using it as a metrology technique. Moreover, it could be interesting to couple the technique with HRXRD measurement. The approach to control SiGe condensation process on FD‐SOI might suggest interesting experiment. (© 2015 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)

Combining metrology techniques for in-line control of thin SiGe:B layers

A study performed to evaluate the benefits of combining techniques to improve the overall metrology of thin silicon germanium (SiGe) epitaxial layers doped with boron is presented. A specifically designed set of wafers was processed and measured by different in-line metrology tools and characterization techniques. This study describes the best strategy for combining metrology techniques in order to reliably determine dopant concentration and Ge composition measurement of the layers. It demonstrates that combined metrology enables key improvements in manufacturing and engineering environments.

Low-Temperature Deposition of Thin Si, Ge, and SiGe Films Using Reducing Activity of Ballistic Hot Electrons

It is shown that a wet process for thin Si and Ge films deposition based on the ballistic electron injection into solutions is available for SiGe. A nanocrystalline silicon (nc-Si) diode is composed of a thin Au (10 nm)/Ti (1 nm) film surface electrode, nc-Si layer (~1 µm), n+-Si substrate, and back contact. The electrochemical effect of ballistic hot electrons was confirmed by cyclic voltammetry analyses. Electrons are emitted from the nc-Si device on which a very small amount of SiCl4+GeCl4 solutions is dripped. After the emitter operation, thin SiGe films are deposited on the emitting surface with neither byproducts nor contaminations as in the case of thin Si and Ge films deposition. Based on the structural and compositional characterizations of deposited SiGe films, the specific features of this reduction-induced deposition mode are discussed in comparison with the conventional processes.

Low-Temperature Deposition of Thin Si, Ge, and SiGe Films Using Reducing Activity of Ballistic Hot Electrons

Quantum-sized nanocrystalline Si (nc-Si) dots behave as a drift layer which efficiently generates ballistic hot electrons. This is due to little phonon scattering losses in nc-Si at the early stage of injection and subsequent multiple-tunneling cascade through nc-Si dots chain interconnected with thin oxides [1]. At a sufficient electric field, generated ballistic hot electrons are ejected through the surface electrode. In solutions, the nc-Si emitter operates as an active electrode supplying highly reducing electrons. This is applicable to deposition of thin films of metals [2], Si [3], and Ge [4]. Details of this thin film deposition scheme based on the ballistic reduction effects is discussed here including the availability for the deposition of thin Ge and SiGe films.The nc-Si emitter is a kind of MIS diode consisting of a thin film surface electrode, a nanosilicon layer (~1 μm thick), a crystalline silicon wafer substrate, and a back contact. The nc-Si layer includes parallel chains of quantum-sized nanosilicon dots (~3 nm in mean diameter) interconnected with tunnel oxides. When a positive voltage is applied to the surface electrode, electrons injected from the substrate into the nc-Si layer are accelerated toward the outer surface, and then some of them are emitted from the surface electrode as ballistic hot electrons [5]. This planar cold cathode emits energetic and directional electrons. The kinetic energy of electrons can be controlled by the applied voltage. At applied voltages of 15-20 V, for instance, the mean energy of output electrons varies from 5 to 7 eV.Besides in vacuum, the nc-Si emitter operates in atmospheric-pressure gases and even in solutions. Since electrons with an extremely high and electrochemical activity are supplied at relatively low applied voltage, positive ion species are directly reduced. Following the experimental confirmation of the usefulness in aqueous solutions as means for H2 generation and pH control, it has been demonstrated that the ballistic hot electron injection into metal-salt solutions leads to the deposition of thin metal (Cu, Ni, Co, Zn, and so on) films without using any counter electrodes.After the device is mounted in a N2 gas filled glove box, a small amount (5~10 μl) of SiCl4, GeCl4, or their mixture (1:1 in volume) was dripped onto the emission surface, and then the emitter was driven at V b=10-15 V. After the emitter operation for several min without using any counter electrodes, thin films were uniformly deposited on the emitting area in the same way as the previous dipping method. The structure and composition of the deposited films were investigated by transmission electron microscope (TEM), scanning electron microscope (SEM), atomic force microscope (AFM), energy dispersive X-ray (EDX) spectra, X-ray photoelectron spectroscopy (XPS), and secondary ion mass spectroscopy (SIMS).In accordance with TEM analyses, the deposited films are amorphous. The observed EDX spectra indicate that the respective deposited films are composed of Si, Ge, and SiGe. The contamination signals of Cl were below the detection limit of XPS measurements. The result of SIMS of thin SiGe films, the compositional ratio of Si to Ge was about 0.9:0.1. This can be controlled by changing the mixture ratio of SiCl4+GeCl4 solution.In contrast to the electro-plating based on exchange of thermalized electrons, the ballistic electro-reduction proceeds with neither Cl2 evolution nor byproducts generation at the counter electrode. Despite a significantly large electrochemical window between the reduction (Si/Si4+) and oxidation (Cl2/Cl-) potentials, injected electrons have energies sufficient enough for unilateral reduction. Being a low-temperature and clean process, this ballistic electro-reduction mode is attractive as an alternative approach for fabrication of group-IV thin-films, multilayered nanostructures, and devices. This work was partially supported by the JSPS through a Grant-in-Aid for Scientific Research and the FIRST Program and by the NEDO through the R&D Project.

Evaluation of Anisotropic Biaxial Stress in Thin Strained-SiGe Layer Using Surface Enhanced Raman Spectroscopy

Introduction Silicon germanium (SiGe) is recognized as a high mobility channel material for the next-generation transistors in place of Si. Nowadays, various future devices using SiGe are being developed [1]. The accurate evaluation of strain (stress) is essential to realize future devices using SiGe. However, the evaluation of stress in thin SiGe layer is difficult because of poor signal embedded in those from huge amount of thick Si substrate [2]. We have previously reported that relatively weak TO phonon excitation in strained SiGe by oil-immersion Raman spectroscopy [3]. We also reported that the evaluation of anisotropic biaxial stress in strained Si on relaxed SiGe layer by exciting longitudinal optical (LO) and transversal optical (TO) phonons using surface enhanced Raman spectroscopy (SERS) [4]. In this study, the SERS measurements were performed to excite the TO phonon in strained SiGe layer more efficiently. Experiment The thin SiGe layer on Si substrate with approximately 30% Ge concentration was used as the sample. The thickness of the SiGe layer was approximately 38 nm. Undecane (C11H24) was used for the solvent of Ag nanoparticles. After spin-coating the Ag nanoparticles on the SiGe surface, the sample was sintered at 190 ›C for 5 min. The average diameter of Ag particles was approximately 30 nm (nominal value). Oil-immersion lens was used to enhance the SERS effect. The numerical aperture (NA) was 1.4 and the refraction index n was 1.5. On the other hand, in the conventional measurement, NA and n were 0.7 and 1.0, respectively. The wavelength of the excitation light source and the focal length of the spectroscope were 532 nm and 2,000 mm, respectively. Results and Discussion Fig. 1 shows the SEM image of the SiGe surface with the Ag nanoparticles. Fig. 2 shows Raman spectra from strained SiGe on the Si substrate coated (w/ SERS) and uncoated (w/o SERS) by the Ag nanoparticles. These spectra were normalized by the Si substrate peak at 520 cm-1. The relative intensity of the SiGe peak was dramatically enhanced and the peak position of SiGe shifted toward a lower wavenumber. Furthermore, the enhanced Raman spectrum was clearly attributed to not only the oil-immersion measurement but also the SERS effect. Fig. 3 shows the peak of strained SiGe obtained by the SERS measurement after the subtraction of the Si substrate peak from the raw data. Both TO and LO phonon components were clearly extracted in fig. 3. From these Raman shift values, the anisotropic biaxial stress can be calculated by the relationship between stress and Raman with the use of phonon deformation potentials (PDPs) and elastic compliances [4,5,6]. As a result, σxx = -2.13 and σyy= -2.21 GPa were obtained. From the results, it was confirmed that the TO phonon was able to be efficiently excited by the SERS. We concluded that the shift on the low wavenumber side was definitely attributed to the TO phonon excitation. The TO/LO phonon excitation allows us to evaluate anisotropic biaxial stress in thin strained-SiGe. Acknowledgement This study was partially supported by the Japan Society for the promotion of Science through a Grant-in-Aid for Scientific Research B (No. 24360125) and Funding program for World-Leading innovative R&D on Science and Technology.

(Invited) Ballistic Hot Electron Effects in Nanosilicon Dots and Their Photonic Applications

The efficient generation of ballistic hot electrons in nanosilicon dots under an electric field is based on the intrinsic carrier transport therein. Due to suppressed phonon scattering losses followed by enhanced tunneling rate, electrons become hot at the early stage of injection [1]. Generated ballistic hot electrons can be utilized either inside or outside the nanosilicon dot layer. The topics on this effect are discussed here toward possible photonic applications. The nanosilicon device is a kind of MIS diode consisting of a thin film surface electrode, a nanosilicon layer (~1 μm thick), a crystalline silicon wafer substrate, and a back contact. The nanosilicon layer includes parallel chains of quantum-sized nanosilicon dots (~3 nm in mean diameter) interconnected with tunnel oxides. When a positive voltage is applied to the surface electrode, electrons injected from the substrate into the nanosilicon layer are drifted toward the outer surface, and then some of them reach the surface electrode as ballistic hot electrons.One possible application of this effect is the avalanche photoconduction by sequential impact ionization in nanosilicon dots. Actually, the photo-carriers multiplication effect was observed in thin oxidized nanosilicon diodes under the reverse bias condition [2]. For a monochromatic near-uv light incidence at low temperatures (e.g., 77 K), the photoconduction quantum efficiency was increased up to 2500% at an external electric field of 9×105 V/cm. The experimental data on the temperature, electric field, and sample thickness dependencies of the photocurrent suggest that the field-induced avalanche multiplication of photo-excited carriers occurs inside the nanosilicon dot layer. From theoretical analyses of carrier dynamics [3], it has been clarified that the impact ionization rate is significantly enhanced in nanosilicon dots compared with in bulk silicon owing to the efficient transition between quantized discrete energy states and the enhanced Coulomb interaction in nanosilicon dots. The threshold electron energy of impact ionization is decreased in realistic nanosilicon dots with disordered surface structures [4]. These facts provide useful information for the development of efficient photo-sensors and photovoltaic cells.Ballistic hot electrons generated in the nanosilicon layer uniformly ejects to outside by tunneling through the thin surface electrode [5]. The most characteristic feature of this emission phenomenon is the high kinetic energy of electrons and its controllability. At applied voltages of 15-20 V, for instance, the mean energy of output electrons varies from 5 to 7 eV. No conventional cold cathodes can emit such energetic electrons. Being a supplier of electrons with an extremely high physical and electrochemical activity, this emitter is available for the operation in every media: vacuum, atmospheric gases, and solutions.In vacuum, this device is applicable to the exposure source for parallel EB lithography [6]. By integrating the emitter array with active-matrix CMOS driver circuit and combining with focusing electron optics system, alternative advanced nanofabrication technology would be developed. Another promising application in vacuum is a probing source for an extremely high-sensitivity image pick-up.The usefulness of the nanosilicon ballistic emitter in atmospheric gases has been demonstrated in air and in Xe gases as a negative ion source and a vacuum-ultraviolet (VUV) light generator, respectively. The former relates to the dissociative hot electron attachment on O2 molecules. In the latter, the output electron energy match well with the internal excitation of Xe gas molecules followed by VUV emission without any impact ionizations.This emitter acts even in solutions as an active electrode which supplies highly reducing electrons. Based on the experimental confirmation of the usefulness in aqueous solutions for H2 generation and pH control, it has been demonstrated that the operation of the emitter in metal-salt solutions is available for depositing thin metal (Cu, Ni, Co, Zn, and so on) films without using any counter electrodes.In contrast to the exchange of thermalized electrons, the ballistic electro-reduction scheme is effective in SiCl4 and GeCl4 solutions. When driven in these solutions, thin Si and Ge films are deposited uniformly on the emitting surface [7]. As in the case in metal-salt solutions, injected energetic electrons can directly reduce Si4+ and Ge4+ ions at the interface leading to the nuclei formation and the subsequent film growth with neither contaminations nor byproducts. Because of a large electrochemical window, it is difficult to get uniform thin Si and Ge films by electroplating. The deposition rate in this unilateral electro-reduction process is comparable to that in the conventional dry process. The structural analyses indicate that the deposited thin Si and Ge films are of amorphous. Visible photoluminescence was observed in ultra-thin Si films. In addition, it is possible to deposit thin SiGe films by the operation in mixture (SiCl4+GeCl4) solutions. Since the ballistic electro-reduction is an alternative clean approach, this is attractive for the low-temperature fabrication of thin-film and multilayered photoelectronic devices.This work was partially supported by the JSPS through a Grant-in-Aid for Scientific Research and the FIRST Program and by the NEDO through the R&D Project.

Practical aspects of strain measurement in thin SiGe layers by (0 0 4) dark-field electron holography in Lorentz mode

Dark-field electron holography (DFEH) is a powerful transmission electron microscopy technique for mapping strain with nanometer resolution and high precision. However the technique can be difficult to set up if some practical steps are not respected. In this article, several measurements were performed on thin Si(1−x)Gex layers using (004) DFEH in Lorentz mode. Different practical aspects are discussed such as sample preparation, reconstruction of the holograms and interpretation of the strain maps in terms of sensitivity and accuracy. It was shown that the measurements are not significantly dependent on the preparation tool. Good results can be obtained using both FIB and mechanical polishing. Usually the most important aspect is a precise control of the thickness of the sample. A problem when reconstructing (004) dark-field holograms is the relatively high phase gradient that characterises the strained regions. It can be difficult to perform reconstructions with high sensitivity in both strained and unstrained regions. Here we introduce simple methods to minimise the noise in the different regions using a specific mask shape in Fourier space or by combining several reconstructions. As a test, DFEH was applied to the characterization of eight Si(1−x)Gex samples with different Ge concentrations. The sensitivity of the strain measured in the layers varies between 0.08% and 0.03% for spatial resolutions of 3.5–7nm. The results were also compared to finite element mechanical simulations. A good accuracy of ±0.1% between experiment and simulation was obtained for strains up to 1.5% and ±0.25% for strains up to 2.5%.

Reduction of Structural Defects in Ge Epitaxially Grown on Nano-Structured Si Islands on SOI Substrate

One way to further increase performance and/or functionality of Si micro-and nanoelectronics is the integration of alternative semiconductors on silicon (Si). We studied the Ge/Si heterosystem with the aim to realize a Ge deposition free of misfit dislocations and with low content of other structural defects. Ge nanostructures were selectively grown by chemical vapor deposition on periodic Si nanoislands (dots and lines) on SOI substrate either directly or with a thin (about 10 nm) SiGe buffer layer. The strain state of the structures was measured by different laboratory-based x-ray diffraction techniques. It was found that a suited SiGe buffer improves the compliance of the Si compared to direct Ge deposition; plastic relaxation during growth can be prevented, and fully elastic relaxation of the structure can be achieved. Transmission electron microscopy confirms that the epitaxial growth of Ge on nanostructured Si is free of misfit dislocations.

Heteroepitaxial growth of Ge on compliant strained nano-structured Si lines and dots on (001) silicon on insulator substrate

On the way to integrate lattice mismatched semiconductors on Si(001) we studied the Ge/Si heterosystem with the aim of a misfit dislocation free deposition that offers the vision to integrate defect-free alternative semiconductor structures on Si. Periodic Ge nano-structures (dots and lines) were selectively grown by chemical vapor deposition on Si nano-islands on silicon on insulator substrate with a thin (about 10nm) SiGe buffer layer between Si and Ge. The strain state of the structures was measured by grazing incidence and specular diffraction using laboratory-based X-ray diffraction technique. The SiGe improves the compliance of the Si compared to direct Ge deposition, prevents plastic relaxation during growth, and allows elastic relaxation before Ge is deposited on top. As a result, an epitaxial growth of Ge on Si fully free of misfit dislocations was achieved.

X-ray characterization of Ge dots epitaxially grown on nanostructured Si islands on silicon-on-insulator substrates

On the way to integrate lattice mismatched semiconductors on Si(001), the Ge/Si heterosystem was used as a case study for the concept of compliant substrate effects that offer the vision to be able to integrate defect-free alternative semiconductor structures on Si. Ge nanoclusters were selectively grown by chemical vapour deposition on Si nano-islands on silicon-on-insulator (SOI) substrates. The strain states of Ge clusters and Si islands were measured by grazing-incidence diffraction using a laboratory-based X-ray diffraction technique. A tensile strain of up to 0.5% was detected in the Si islands after direct Ge deposition. Using a thin (∼10 nm) SiGe buffer layer between Si and Ge the tensile strain increases to 1.8%. Transmission electron microscopy studies confirm the absence of a regular grid of misfit dislocations in such structures. This clear experimental evidence for the compliance of Si nano-islands on SOI substrates opens a new integration concept that is not only limited to Ge but also extendable to semiconductors like III-V and II-VI materials.

Very Low Electron Density in Undoped Enhancement-Mode Si/SiGe Two-Dimensional Electron Gases with Thin SiGe Cap Layers

We report the lowest electron density (4.9×1010 cm-2 and 1.1×1011 cm-2) and high mobility (~400,000 cm2/Vs and ~200,000 cm2/Vs) of undoped enhancement-mode Si/SiGe two-dimensional electron gases comparing to samples previously reported with similar thin SiGe cap thickness (55nm and 27nm). The dominant scattering mechanism over a wide range of two-dimensional electron density in both samples is the scattering from remote charges at oxide/silicon interface. In addition, a clear metal-insulator transition is observed in the sample with a 27-nm SiGe cap.

Effective Condensation Process for Higher Ge Concentration and Thin SiGe layer-on-insulator Substrates in Advanced High Mobility MOSFETs

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Thermal reliability of thin SiGe epilayers

The SiGe heterostructures can play a role that drastically enhances the carrier mobility of SiGe heterodevices, such as strained Si metal oxide semiconductor field effect transistors. However, it is difficult to access the both issues, that is, the propagation of the dislocation and thermal reliability of annealed SiGe films. In this study, we used ultrahigh-vacuum chemical vapor deposition to grow Si0.8Ge0.2 films (ca. 200nm thick for heteroepitaxy) epitaxially on bulk Si. The samples were subsequently furnace-crystallized at temperatures of 800, 900, and 1000°C. We used nanoscratch techniques to determine the frictional characteristics of the SiGe epilayers under various ramping loads and employed atomic force microscopy to examine their morphologies after scratching. From our investigation of the pile-up phenomena, we observed significant cracking dominating on both sides of the scratches on the films. The SiGe epilayers films that had undergone annealing treatment possessed lower coefficients of friction, suggesting higher shear resistances.