Thin SiGe Research Articles

Thermal stability of supercritical thickness-strained Si layers on thin strain-relaxed buffers

The structural reaction of sub- and supercritical thickness-strained Si layers on novel thin SiGe strain-relaxed buffers (SRBs) during high-temperature annealing used in device fabrication is investigated. Atomic force microscopy, chemical defect etching, scanning electron microscopy, optical profilometry, optical microscopy, and Raman spectroscopy are used to study defect formation and morphology on thin and thick Si0.82Ge0.18 SRBs grown using a C-induced relaxation technique. For subcritical thickness layers, the defect density was found to be similar in both thin and thick SRBs and both structures responded similarly to annealing, indicating good thermal stability of thin SRB technology. The root-mean-square surface roughness of strained Si grown on thin SRBs was ∼50% lower than on similarly grown thick SRBs and conventional step-graded thick SRBs, and was robust during annealing. The impact of strained Si layer thickness on surface morphology is also analyzed. Using detailed filtering techniques, macro- and microroughness are distinguishable. For the first time, we show that exceeding the critical thickness has a greater impact on microroughness than on macroroughness. Whereas macroroughness is similar for sub- and supercritical thickness-strained Si layers, the microroughness is ∼2× larger in supercritical layers than in subcritical thickness layers. Prominent surface defects were detected on supercritical strained Si layers. The defects align with the cross-hatch morphology and double in density following annealing. It is proposed that the defects originate from localized threading dislocations assisted by further strain relaxation in the metastable strained Si layers. This is substantiated through the observation of stacking faults in the strained Si. In contrast, surfaces of subcritical thickness-strained Si layers on thin SRBs are defect-free.

Growth of Ge Layer on Relaxed Ge-Rich SiGe by Ultrahigh Vacuum Chemical Vapor Deposition

The paper describes the growth of a germanium (Ge) film on a thin relaxed Ge-rich SiGe buffer. The thin Ge-rich SiGe buffer layer was achieved through a combination of ultrahigh vacuum chemical vapor deposition (UHVCVD) SiGe epitaxial growth and SiGe oxidation. A lower Ge content strained SiGe layer was first grown on the Si (001) substrate and then the Ge mole fraction was increased by oxidation. After removal of the surface oxide, a higher Ge content SiGe layer was grown and oxidized again. The Ge mole fraction was increased to 0.8 in the 50 nm thick SiGe layer. Finally a 150 nm thick pure Ge film was grown on the SiGe buffer layer using the UHVCVD system. This technique produces a much thinner buffer than the conventional compositionally graded relaxed SiGe method with the same order of magnitude threading dislocation density.

Quantifying self-heating effects with scaling in globally strained Si MOSFETs

Electrical results are presented for deep submicron strained Si MOSFETs fabricated on both thick and thin SiGe strain relaxed buffers, SRBs. For the first time thin SRB devices are shown to offer the same performance enhancements as thick SRB devices. The reduction in performance enhancement with device scaling widely reported in the literature has also been investigated. Correcting for dynamic self-heating effects using ac measurements, the enhancements seen in long channel devices are maintained down to short channel lengths, demonstrating the scalability of SRB technology. Thermal resistances have been measured experimentally and compared with analytical models. The thermal resistance for devices on the thin SRBs is reduced by 50% compared with devices on thick SRBs. Finally, a comparison of self-heating effects in MOSFETs fabricated on SOI and Si 0.8Ge 0.2 SRBs provides insight into the challenges ahead as power densities continue to increase.

Fabrication of SiGe Virtual Substrates by Ion Implantation Technique

We have developed a new SiGe virtual substrate fabrication technique where pre-ion-implantation is employed. In this method, prior to growth of SiGe layers, defects are intentionally introduced in the vicinity of Si substrate surfaces via implantation of relatively heavy ions, such as Ar+, Si+ and Ge+. Thin SiGe layers are grown on the ion-implanted Si substrates and the subsequent annealing considerably enhances the strain relaxation of the SiGe layers due to implantation-induced defects working as dislocation generation sources. As a result, extremely thin (100 nm) and largely-relaxed SiGe layers with atomically flat surfaces and very uniform strain distribution are obtained. These thin SiGe virtual substrates can be applied to the fabrication of strained-Si nMOSFETs and the significant mobility enhancement over the bulk Si device is obtained. These results clearly indicate that the ion implantation technique is very promising for realization of high-performance Si/Ge heterodevices based on SiGe virtual substrates.

Ge on Si Photodiodes for Si CMOS Monolithic Optical Receivers

We report a Ge growth technique on Si using thin SiGe buffer layers and also discuss photodiodes fabricated on the Ge for Si CMOS monolithic optical receiver applications. The effectiveness of thin SiGe buffer layers in terminating threading dislocations and reducing photodiode dark current for Ge epitaxially grown on Si (001) has been investigated for Ge photodiodes. The dark current of Ge on Si photodiodes can be reduced by over an order of magnitude by incorporating two different composition SiGe buffer layers. A backside- illuminated photodetector has been fabricated with the dark current as low as 3.6 mA/cm2 at 1 V reverse bias. To improve the speed of the photodiode, a device with thinner SiGe buffer layers was demonstrated and achieved 21.5 GHz bandwidth at 1.31 mm, resulting in a record high efficiency-bandwidth product of 12.9 GHz.

Strained Si n-channel metal-oxide-semiconductor field-effect transistors formed on very thin SiGe relaxed layer fabricated by ion implantation technique

Strained Si n-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) were fabricated on the Si0.83Ge0.17 relaxed thin layer formed by ion implantation technique. Although the SiGe thickness was as small as 100nm, the relaxation was highly enhanced thanks to the pre-ion-implantation into the Si substrate and the strained Si channel with very smooth surface was obtained. A nMOSFET was fabricated in this structure and 100% drive current improvement and 60% mobility enhancement over the control Si MOSFET were achieved. This indicates that the ion implantation technique is very promising for realization of relaxed-SiGe-based devices with very high performances.

Impact of strain and channel orientation on the low-frequency noise performance of Si n- and pMOSFETs

Mobility and low-frequency (LF) noise were studied in tensile strained Si n- and pMOSFETs fabricated on relaxed SiGe virtual substrates. Both the impact of the channel orientation (〈1 1 0〉 or 〈1 0 0〉 on (1 0 0) Si) and the tensile strain were carefully investigated. Two types of virtual substrates were used; a thin relaxed SiGe layer (20% Ge) and a thick one (27% Ge). The strained Si nMOSFETs fabricated on the thin substrate showed similar LF noise level as in the reference devices, whereas the thick substrate caused severely increased LF noise in the nMOSFETs. The latter was linked to the higher Ge concentration and explained by possible misfit dislocations and increased defect densities, likely resulting from strain relaxation caused by ion implantation damage. On the other hand, considerably lower LF noise was achieved in the pMOSFETs on the thick SiGe. The channel orientation was not found to have a significant influence on the LF noise performance in any of the studied devices.

Strained Silicon-On-Insulator - Fabrication and Characterization

SSOI substrates were successfully fabricated using He+ ion implantation and annealing to relax thin (< 500nm) SiGe buffer layers, bonding and layer transfer processes to realize strained-Si layers onto oxide layers. The reduced thickness of the SiGe buffer possess numerous advantages such as reduced process costs for epitaxy and for reclaim of the handle wafer if the layer splitting is initiated in the SiGe/Si interface. The electron mobilities in the fabricated SSOI layers were measured using transistors with different gate lengths. An electron mobility of ~530 cm2 /Vs was extracted, being much higher than in non-strained SOI substrates. Furthermore, an 80% drive current (IDSAT) improvement has been measured for long channel devices.

Compact Analytical Threshold-Voltage Model of Nanoscale Fully Depleted Strained-Si on Silicon–Germanium-on-Insu lator (SGOI) MOSFETs

In this paper, a physically based analytical threshold-voltage model is developed for nanoscale strained-Si on silicon-germanium-on-insulator MOSFETs for the first time, taking into account short-channel effects. The model is derived by solving the 2-D Poisson equation in strained-Si and SiGe layers. The effects of various important device parameters like strain (Ge mole fraction in the SiGe layer), body doping, gate workfunction, strained-Si thin film and SiGe layer thickness, etc., has been considered. We have demonstrated that increasing strain in order to enhance device performance can lead to undesirable threshold-voltage rolloff. The model is found to agree well with the 2-D simulation results

Effectiveness of SiGe Buffer Layers in Reducing Dark Currents of Ge-on-Si Photodetectors

The effectiveness of thin SiGe buffer layers in terminating threading dislocations and reducing photodiode dark current for Ge epitaxially grown on Si (001) has been investigated. The structural morphology of the films was studied by atomic force microscopy and transmission electron microscopy. The dark current of Ge on Si photodiodes can be reduced by over an order of magnitude by incorporating two different composition SiGe buffer layers. The origin of dark current and the effectiveness of thermal annealing the SiGe layers were also studied

Nanocavity Buffer Induced by Gas Ion Implantation in Silicon Substrate for Strain Relaxation of Heteroepitaxial Si1-xGex/Si Thin Layers

AbstractTo weight the importance of a nanocavity buffer in a SiGe deposition substrate, some P type (001) FZ Si wafers are implanted (A samples) or not (B samples) at room temperature with 5×1016 He+ cm–2 at 10keV. They are annealed at 700°C for one hour to form a nanocavity layer close to the Si surface. Then, the wafers are carefully chemically cleaned in a clean room to remove both organic and metallic impurities from the surface. They are coated either by 210 nm (A) or 430 nm (B) Si1−xGex (x=0.20±0.02) alloy grown at 575°C for 0.42 hour by low pressure chemical vapor deposition (LP-CVD) with a growth rate of 8 to 17 nm.mn−1. Both kinds of samples are studied by cross section transmission electron microscopy, X-rays diffraction, Rutherford backscattering, atomic force microscopy and etch pit counts. The association of these techniques demonstrates that the thin SiGe layer which is deposited on sample A is fully relaxed and that the threading dislocation density (estimated to hardly reach 4×103cm−2) is at least one order of magnitude lower than what is obtained so far using ion implantation assistance in SiGe layer growth on Silicon. The roughness of the SiGe surface is low enough to stand a further Si epitaxy. Nevertheless, the mechanism involved responsible for the threading dislocation annihilation and/or confinement is still unclear.

A new method of fabricating strained Silicon materials

Strain-relaxed SiGe virtual substrates are of great importance for fabricating strained Si materials. Instead of using graded buffer method to obtain fully relaxed SiGe film, in this study a new method to obtain relaxed SiGe film and strained Si film with much thinner SiGe film was proposed. Almost fully relaxed thin SiGe buffer layer was obtained by Si/SiGe/Si multi-structure oxidation and the SiO 2 layer removing before SiGe regrowth. Raman spectroscopy analysis indicates that the regrown SiGe film has a strain relaxation ratio of about 93% while the Si cap layer has a strain of 0.63%. AFM shows good surface roughness. This new method is proved to be a useful approach to fabricate thin relaxed epilayers and strain Si films.

Strain relaxation in thin SiGe epilayers doped with carbon

The possibility of obtaining a heterosystem consisting of the upper partially strained and lower relaxed sublayers by stepwise in situ doping of SiGe layers by carbon is considered. The properties of the as-grown and annealed samples are studied by means of Raman spectroscopy and atomic force microscopy. The degree of strain relaxation in the as-grown layers was derived from the Raman spectra. The Si0.7−yGe0.3Cy layer was shown to be stable to annealing up to 700°C. Moreover, the strain relaxes during annealing not homogenously over the whole structure but in a layer-by-layer way. The segregation of carbon atoms is observed for as-grown Si1−x−yGexCy layers in the near-substrate regions.

From Thin Relaxed SiGe Buffer Layers to Strained Silicon Directly on Oxide

Thin relaxed SiGe buffer layers with Ge contents of 23at% and 26at% and thicknesses between 150 to 180 nm on Si(100) terminated with 6 nm Si were made by He ion implantation and annealing. Subsequent overgrowth of the thin buffers with thin strained Si cap layers with SiGe and strained Si reduced the threading dislocation and pile-up densities significantly. Best results were achieved for high temperature SiGe overgrowth with a thickness of 200nm and Ge contents lower than the effective Ge content of the buffer. Threading dislocation densities as low as 1x105 cm-2 and dislocation pile-up densities of 10 cm-1 were determined. Strained silicon on insulator wafers were produced by wafer bonding. Wafer splitting was done by H ion implantation and annealing. The strain of the layers was measured by Raman spectroscopy revealing a strain of 0.66% in the tensile strained Si on the partially relaxed Si0.77Ge0.23 buffers.

Integration of SiGe to MEMS applications

SiGe offers new advantages in MEMS technologies. The excellent electronic and optoelectronic properties of SiGe alloys are of main interest for MEMS and NEMS. SiGe combines the electronic properties of Si and Ge having different band structures. Bandgap engineering allows the realization of different electronic and optical properties depending on the composition of the alloy and on the strain in the layer. This gives the opportunity to create new components and microsystems using a silicon-based technology and to replace III-V compound materials. Depending on the growth of SiGe layers tensile or compressive stress is caused in the layers making it possible to create prestressed or deformable elements. Strain engineering allows the realization of numerous microsystems. Combining, for instance, thin SiGe and Si layers result in deformable structures used as nanometer-range building blocks for future electronic and mechanical nanodevices.

Study of the Surface Cleaning of GOI and SGOI Substrates for Ge Epitaxial Growth

An effective wet cleaning process, optimized for low temperature Ge epitaxy on thin Ge or SiGe structures with reduced surface roughening, is proposed. It is found that the HF+HCl cleaning is the most effective wet cleaning method that is applicable to the low temperature thermal cleaning. It is also found that temperature of the thermal cleaning appropriate for thin Germanium on Insulator (GOI) substrates is approximately 450ºC. Moreover, the successful formation of the strained-GOI structures is demonstrated by applying these wet and thermal cleaning processes to thin Silicon-Germanium on Insulator (SGOI) substrates.

Silicon-Germanium Heterostructure-on-Insulator Formed by Ge+ Ion Implantation and Hydrogen Transfer

Using bulk silicon can be ended for 32 nm technological nodes. New type of substrates needs for further scaling in CMOS microelectronics. We speculate that these new type of materials will be semiconductor heterostructure on insulator (SHI) compatible with current silicon planar CMOS technology. Joint semiconductor material stack placed on cheap amorphous dioxide is presented. First of all thin film SiGe heterostructure properties is considered. It was obtain using Ge ion implantation in dioxide with followed Ge segregation to the directly bonded interface between silicon and silicon dioxide wafers. The method is also compatible with A3B5 thin film formation.

Comparison of SiGe Virtual Substrates for the Fabrication of Strained Silicon-on-Insulator (sSOI) Using Wafer Bonding and Layer Transfer

Different methods of preparing sSOI wafers have been analyzed. The initial virtual substrate wafers are characterized by a 17 - 20 nm thick strained silicon layer grown either on a thick relaxed SiGe layer on a graded buffer or on a thin SiGe buffer relaxed by He implantation. Bonding and layer transfer experiments using different oxide layers proved that strained silicon layers are completely transferred if designed PE-CVD oxide layers were used. For both types of virtual substrates the oxide layers are deposited on top of the strained silicon and bonded to non-oxidized (blank) silicon wafers. A perfect layers transfer is obtained for virtual substrates having thick SiGe buffer layers (type A) even at 350ºC, while annealing at 450ºC is required for substrates with thin SiGe buffer layers (type B). The lower annealing temperature for substrates of type A is caused by the lower activation energy for blistering. The hydrogen implantation is here into the SiGe. For type B substrates the hydrogen implantation is into the underlying Si requiring a higher temperature for layer splitting (higher activation energy for Si).

Ge Selective Epitaxial Growth with Ultra Thin SiGe Buffer Layer

In this study, we introduced another very thin SiGe layer that was selectively grown on the Si buffer layer prior to the ultra- thin Si0.5Ge0.5 buffer growth. As a result, selective epitaxial growth of Ge film with good crystalline quality was realized without increasing intermediate layer thickness or thermal budget significantly. This technique is expected to be applicable for the Ge channel formation and other application that require selective Ge film formation with low thermal budget. The mechanism of selectivity enhancement by the first SiGe layer as well as its influence on crystalline quality of the Si0.5Ge0.5 buffer layer and Ge epitaxial layer above will be discussed in the presentation.

Control of Self-Heating in Thin Virtual Substrate Strained Si MOSFETs

This paper presents the first results and analysis of strained Si n-channel MOSFETs fabricated on thin SiGe virtual substrates. Significant improvements in electrical performance are demonstrated compared with Si control devices. The impact of SiGe device self-heating is compared for strained Si MOSFETs fabricated on thin and thick virtual substrates. This paper demonstrates that by using high-quality thin virtual substrates, the compromised performance enhancements commonly observed in short-gate-length MOSFETs and high-bias conditions due to self-heating in conventional thick virtual substrate devices are eradicated. The devices were fabricated with a 2.8-nm gate oxide and included NiSi to reduce the parasitic series resistance. The strained layers grown on the novel substrates comprising 20% Ge did not relax during fabrication. Good on-state performance, off-state performance, and cross-wafer uniformity are demonstrated. The results show that thin virtual substrates have the potential to circumvent the major issues associated with conventional virtual substrate technology. A promising solution for realizing high-performance strained Si devices suitable for a wide range of applications is thus presented