Thin Gate Dielectrics Research Articles

Deep sub-micron gate diamond MISFETs

The basic characteristics of the short channel FETs have been investigated for the high-frequency performance of the diamond MISFETs. The deep sub-micron gate (0.23–0.5 μm) diamond MISFETs were fabricated on an H-terminated diamond surface. The short channel effect is well suppressed utilizing thin gate insulator. Accordingly, the transconductance is improved by reduction of gate length down to 0.2 μm. This tendency is observed in diamond MISFETs for the first time. Maximum transconductance reaches 71 mS/mm in DC mode and 51 mS/mm in AC mode. The f T of 40 GHz is expected in 0.2 μm gate MISFETs as a result.

High quality atomic-layer-deposited ultrathin Si-nitride gate dielectrics with low density of interface and bulk traps

Interface trap and bulk trap densities of atomic-layer-deposited (ALD) Si-nitride dielectrics have been evaluated by bipolar-voltage-pulse-induced current and electrical-stress-induced leakage-current measurements, respectively. In comparison with the conventional SiO2 dielectrics, significantly lower (∼1/3) interface trap density near the conduction band edge is observed in the ALD Si-nitride dielectrics. Moreover, the observed lower interface and bulk trap generations consistently explain the soft-breakdown-free phenomena observed in capacitors with the ALD Si-nitride gate dielectrics. Enhanced dielectric reliability and several other significant features have made the ALD Si-nitride gate dielectrics a front line candidate for extremely thin (equivalent oxide thickness ∼1 nm) gate dielectrics of sub-100-nm technology nodes.

Thermal response of MOCVD hafnium silicate

As complementary metal oxide semiconductor (CMOS) devices continue to scale along the rapid performance and miniaturization pace of Moore’s Law, the unacceptably high direct tunneling leakage current through the thin transistor gate insulator layer is of increasing concern. To this end, gate insulator materials with significantly higher dielectric constants ( k=10–25) continue to be investigated as potential replacements for silicon dioxide, SiO 2 ( k=3.9), and silicon oxynitride. This challenge provides opportunities for integration of a physically thicker film with lower leakage current and with capacitance equivalent to <1.0 nm SiO 2. Local changes in the composition of the candidate material, uncapped metal–organic chemical vapor deposited (MOCVD) hafnium silicate, (HfO 2) x−1 (SiO 2) x , have been evaluated by several techniques, including grazing incidence X-ray diffraction (GI-XRD), time-of-flight secondary ion mass spectroscopy (ToF-SIMS) and high angle annular dark field scanning transmission electron microscopy (HAADF-STEM). Hafnium silicate gate dielectric transistor performance data comparing high- k films with post-deposition anneal (PDA) treatments of NH 3 and N 2 at various process temperatures are presented. Changes in the material microstructure associated with phase segregation and crystallization as a function of Hf silicate composition and anneal temperature have been observed and discussions of the corresponding reaction mechanisms are presented.

The 1/f/sup 1.7/ noise in submicron SOI MOSFETs with 2.5 nm nitrided gate oxide

The low-frequency noise of partially depleted silicon-on-insulator (SOI) MOSFETs is studied in the ohmic regime. In the frequency range 0.7 Hz /spl les/ f /spl les/ 50 Hz, a power spectral density is observed which follows a 1/f/sup n/ law, with n /spl sim/ 1.7 for a broad range of operation conditions. This noise is to be distinguished from the usual 1/f-like noise, occurring at higher frequency for devices with a length smaller than 1 /spl mu/m. From the dependence on the gate voltage and device length, it is concluded that the 1/f/sup 1.7/ noise is of the McWhorter type and, therefore, is generated by carrier exchange between the front channel and traps in the 2.5 nm NO gate oxide. This type of noise is absent in the back-channel or in the gate current. A model will be presented, from which it is derived that the responsible traps are most likely associated with the polysilicon gate/oxide interface and, furthermore, show a steep concentration profile over a small depth range. A similar noise behavior is observed in bulk devices with thin gate dielectrics.

Damascene W/TiN gate MOSFETs with improved performance for 0.1-μm regime

W/TiN gate CMOS technologies with improved performance were investigated using a damascene metal gate process. 0.1-/spl mu/m W/TiN stacked gate CMOS devices with high performance and good driving ability were fabricated successfully by optimizing the W/TiN stacked gate structure, improving the W/TiN gate electrode sputtering technology, and reducing W/TiN stacked gate MOSFET surface states and threshold voltages. A super steep retrograde (SSR) channel doping with heavy ion implantation, /sup 115/In/sup +/ for NMOS and /sup 121/Sb/sup +/ for PMOS, was applied here to obtain a reasonably lower threshold voltage and to suppress short-channel effects (SCEs). Non-CMP technology, used to replace CMP during the damascene metal gate process, was also explored. The propagation delay time of 57 stage W/TiN gate CMOS ring oscillators was 13 ps/stage at 3 V and 25 ps/stage at 1.5 V, respectively. Better performance would be achieved by using Co/Ti salicide source/drain (S/D) and thinner gate dielectrics.

New challenges in thin film transistor (TFT) research

This paper addresses the current trends in research and development for: (1) Thin film transistors (TFTs) on plastic substrates, (2) low-temperature poly-silicon (LTPS) for the pixel TFTs and for row and column drivers on glass, (3) addressing of organic light emitting diodes by silicon TFTs. For these advanced applications of TFTs the relevant issues are: (i) higher electron mobility, (ii) stability, and (iii) defect free, uniform deposition of thin silicon films and gate dielectrics at a high deposition rate (reduced cost). At Utrecht University, we are investigating hot wire (catalytic) chemical vapor deposition (CVD) as a deposition technique for novel TFTs that have a high potential to meet the above mentioned requirements. Bottom gate, inverted staggered TFTs with hot wire CVD (HWCVD) silicon films have been made with an electron mobility of 1.5 cm 2/ V s , and with field effect characteristics that are completely stable under operating conditions. Top gate, coplanar TFTs with polycrystalline silicon (poly-Si) films have been made, which showed a mobility of 4.7 cm 2/ V s . This has been obtained without any post treatment, and the hot wire technology can thus avoid expensive, time-consuming steps such as laser recrystallization as currently used in the production of the latest poly-Si lap top displays. HWCVD is also suitable for the deposition of SiN x :H gate dielectrics. TFTs with a hot wire silicon nitride gate dielectric have been deposited.

Ultrathin Si3N4 Films Deposited From Dichlorosilane For Gate Dielectrics Using Single-Wafer Hot-Wall Rapid Thermal CVD

AbstractUsing a hot-wall rapid thermal system which permits single-wafer processing, thin gate dielectrics consisting of silicon nitride films were fabricated by low pressure chemical vapor deposition (LPCVD). Nitride layers deposited from dichlorosilane (DCS) and ammonia exhibited greatly reduced electrical leakage current compared to silane-based nitride films which are conventionally used in lamp-based single-wafer rapid thermal technology. After a postdeposition anneal, the DCS-based gate dielectric films showed better diffusion barrier properties against boron penetration than silane-based gate dielectrics at a dopant activation temperature of 1000°C.

Plasma nitridation of very thin gate dielectrics

The performance of NMOSFET devices with nitrided gate oxides has been compared using two plasma-based nitridation techniques. Specifically, remote plasma nitridation (RPN) and decoupled plasma nitridation (DPN) of 1.4 nm base oxides were evaluated. It is found that both nitridation techniques give comparable leakage current performance, where 4–10× leakage current reduction can be achieved compared to un-nitrided oxides. The flatband voltages of the DPN-nitrided gate dielectric are larger (more negative) than those of RPN-nitrided gate dielectric, possibly indicating more fixed charge for the DPN process conditions used. The normalized peak transconductance of RPN and DPN-nitrided gate dielectrics depends on the detailed nitridation conditions, but can be comparable to that of un-nitrided oxides. The normalized drive currents are largest for the DPN-nitrided oxides, most likely because of the smaller threshold voltage measured after DPN nitridation. The results suggest that for NMOSFET devices, the two nitridation processes (RPN and DPN), if properly optimized, can give comparable device performance.

Investigation of plasma damage effects on characteristics and reliability of MOS devices with thin gate dielectrics

Device damage due to plasma process-induced charging continues to be a great threat and concern in modern CMOS technologies. This paper investigates NMOS vs. PMOS device sensitivity to plasma charging originating from various processing steps. This dependence is studied with respect to the gate oxide thickness and large antenna devices are used to evaluate device yield, latent damage, and residual effect of charging on device performance and reliability. In addition to results obtained for oxides of 40–90 Å, specific studies are performed to explore the resistance to charging damage in CMOS devices with 50 Å gate oxide grown with various oxidation processes.

Scaling CMOS devices through alternative structures

The conventional wisdom holds that CMOS devices cannot be scaled much further from where they are today because of several device physics limitations such as the large tunneling current in very thin gate dielectrics. It is shown that alternative device structures can allow CMOS transistors to scale by another 20 times. That is as large a factor of scaling as what the semiconductor industry accomplished in the past 25 years. There will be many opportunities and challenges in finding novel device structures and new processing techniques, and in understanding the physics of future devices.

Study of low-frequency charge pumping on thin stacked dielectrics

The application of low-frequency charge pumping to obtain near-interface, or bulk trap densities, on thin stacked gate dielectrics is studied. A review of the theory governing the low-frequency charge pumping technique, developed to extract bulk trap densities from metal-oxide-semiconductor field-effect transistors (MOSFETs) fabricated with thick SiO/sub 2/ dielectrics, is given. In this study, the technique is applied to a series of n-channel MOSFETs fabricated with stacked gate dielectrics. The dielectric stacks were comprised of rapid thermal oxide (RTO) interface layers and rapid thermal chemical vapor deposited (RTCVD) oxynitride layers, which incorporated varying concentrations of nitrogen. The effect of DC tunneling currents on the technique is studied, and a procedure to remove these components from the measured substrate current is outlined. Distortions in the experimentally measured charge pumping current plotted as a function of gate bias is modeled and found to be due to the contribution of bulk traps. Finally, the limitations of applying a model that was originally developed for thick SiO/sub 2/ dielectrics to thin stacked gate dielectrics are discussed.

Fabrication of 0.1 µm channel diamond Metal-Insulator-Semiconductor Field-Effect Transistor

ABSTRACTAnalysis of diamond short channel effect is carried out for the first time. 70 nm channel diamond metal-insulator semiconductor field-effect transistor is realized by utilizing new FET fabrication process on the hydrogen-terminated surface conductive layer. This FET is the shortest gate length in diamond FETs. FETs with thick gate insulator of 35 nm show significant threshold voltage shift and degradation of subthreshold slope S by the gate refining. This phenomenon occurs due to the penetration of drain field into channel. However, the degradation of subthreshold performance and threshold voltage shift are hardly observed in 0.17 µm FET with thin gate insulator 15 nm in thickness.

Hydrogenated amorphous silicon thin-film transistor with a thin gate insulator

Thinning the gate insulator in an hydrogenated amorphous silicon thin-film transistor (a-Si:H TFT) has been studied in a coplanar structure. The threshold voltage decreases with decreasing gate insulator thickness without changing the field effect mobility significantly. The reduction in the threshold voltage is due to the decrease in the charge traps in the SiN/sub x/ and in its film thickness. The coplanar a-Si:H TFT with a gate insulator thickness of 35 nm exhibited a field effect mobility of 0.45 cm/sup 2//Vs and a threshold voltage of 1.5 V. The thickness of the gate insulator can be decreased in the coplanar a-Si:H TFTs because of the planarized gate insulator.

Precise Characterization of Resists and Thin Gate Dielectrics in the VUV Range for 157nm Lithography

AbstractSpectroscopic ellipsometry is one of the most important tools for thin film metrology. It is now intensively used in microelectronics and especially for the microlithographic applications. Instrumentation for the next generation of VUV lithography at 157nm requires special optical setup since oxygen and water are extremely absorbing below 190nm. Recently a new ellipsometer included in a purged glove box to reduce the oxygen and water contamination in the part per million range has been developed. In the VUV range, roughness and interface diffusion become critical since the layer thickness is generally reduced. An independent characterization technique like the grazing x-ray reflectance is then extremely complementary to ellipsometry in this wavelength region. The present paper presents recent results on up to date lithography samples combining the two characterization techniques. Photoresists and gate dielectrics are successively examined.

Emerging oxide degradation mechanisms: Stress induced leakage current (SILC) and quasi-breakdown (QB)

The reliability of thin oxides is a primary concern for the qualification of advanced CMOS, DRAMS and non volatile memory technologies. With the scaling down process the thickness of active dielectrics in CMOS, DRAMs and memory devices has steadily been reduced during the past years. The reduction of the oxide thickness has given rise to the onset of new phenomena for the viewpoint of reliability such as stress induced leakage current (SILC) and quasi-breakdown (QB). This paper intends to present a brief review of these emerging degradation processes which affect the reliability of ultra-thin oxides. The main characteristics and the physics underlying the SILC and QB will be discussed and illustrated with recent experimental results obtained on advanced technologies featuring thin gate dielectrics.

Silicon oxide/silicon nitride dual-layer films: a stacked gate dielectric for the 21st century

Incorporation of nitrogen atoms into ultra thin (<0.3 nm) gate dielectrics (i) reduces defect generation at the Si–SiO 2 interface, (ii) allows use of physically thicker dielectrics when incorporated into oxide–nitride stacked gate dielectrics, and (iii) prevents boron atom transport out of heavily doped p + polycrystalline silicon gate electrodes when nitrided layers are incorporated at the polycrystalline Si-dielectric interface. I demonstrate that nitrogen atoms can be selectively and independently incorporated into different parts of the gate dielectric structure by low-temperature (∼300°C) remote plasma assisted processing followed by low-thermal budget rapid thermal annealing (RTA) yielding state of the art field effect transistors with oxide equivalent thicknesses less than 2 nm.

Electrical characterization of n-channel MOSFETs with oxynitride gate dielectric formed by Low-Pressure Rapid Thermal Chemical Vapor Deposition

This study reports on n-channel MOS transistors using very thin oxynitride gate dielectrics deposited by Low-Pressure Rapid Thermal Chemiical Vapor Deposition (LPRTCVD). The threshold voltage, the transconductance, the fast and slow trap densities, the low field mobility and its reduction factors have been investigated as a function of the nitrogen concentration in the film. The threshold voltage was found to decrease linearly with the nitrogen concentration, primarily because of the increase of the positive insulator charge density. At the same time, it has been shown that the quadratic mobility reduction factor is lower for a LPRTCVD oxynitride (and nearly constant with the nitrogen concentration) in comparison to a thermal oxide. From this high field mobility attenuation, a lower transconductance is then expected for oxynitride-based transistors. Finally, we have shown that the presence of nitrogen in the oxide seems to induce more donor than acceptor traps at the oxynitride-silicon interface.

Low temperature-high pressure grown thin gate dielectrics for MOS applications

In this study we propose high pressure grown oxide (HIPOX) as an alternative low-temperature MOS gate insulator and show that it performs excellently in comparison to other widely reported low-temperature deposited oxides. Our optimized process conditions for HIPOX result in high quality gate dielectric comparable in quality to the standard thermal dry oxide in terms of initial properties as well as under various stress conditions. Sub 100 nm channel length vertical MOSFETs with HIPOX as a gate dielectric are fabricated and characterized to demonstrate the suitability of HIPOX as a low-temperature MOS gate dielectric.

32.1: Invited Paper: Amorphous Silicon Thin‐Film Transistors with Planarized Gate Insulators

AbstractHigh‐performance, amorphous silicon thin‐film transistors (TFTs) with planarized gate insulators have been developed. Such TFTs can adopt thick gate metal, thin active layer and thin gate insulator, therefore are very suitable to the high‐performance, large‐area TFT‐LCDs.

Electrical properties of oxynitride thin films using noise and charge pumping measurements

Slow traps and interface traps density has been measured using low frequency (10 Hz) noise and charge pumping measurements. The study has been carried out on n-channel metal-oxide-semiconductor transistors with ultra thin gate dielectrics prepared by rapid thermal oxidation (RTO) and low pressure rapid thermal chemical vapor deposition. For both deposition methods, the interface trap characteristics have been studied as a function of nitrogen concentration as well as thermal annealing parameters (ambient and temperature). Experimental results have shown that a stacked dielectric combined RTO gate oxide (grown under N 2O) and chemical vapor deposition oxynitride (capping layer with 8% atomic nitrogen concentration), offers a solution for gate dielectrics with thickness ⩾2 nm.