Thin Gate Dielectrics Research Articles

Low-voltage organic thin film transistors with hydrophobic aluminum nitride film as gate insulator

This paper reports on the low-voltage (<5 V) pentacene-based organic thin film transistors (OTFTs) with a hydrophobic aluminum nitride (AlN) gate-dielectric. In this work, a thin (about 50 nm), smooth (roughness about 0.18 nm) and low-leakage AlN gate dielectric is obtained and characterized. The AlN film is hydrophobic and the surface free energy is similar to the organic or the polymer films. The demonstrated AlN–OTFTs were operated at a low-voltage (3–5 V). A low-threshold voltage (� 2 V) and an extremely low-subthreshold swing (� 170 mV/dec) were also obtained. Under low-voltage operating conditions, the on/off current ratio exceeded 10 6 , and the field effect mobility was mobility was 1.67 cm 2 /V s.

Submicron pentacene-based organic thin film transistors on flexible substrates

The authors demonstrate the fabrication of organic thin film transistors (OTFTs) based on pentacene with submicron channels on flexible substrates. Nanoimprint lithography is used for the patterning of the source and drain electrodes and processed directly on the spin-on gate dielectric, the structured gate electrode, and the flexible substrate. The use of sub-100-nm thin organic gate dielectrics enables full drain current saturation for devices with channel lengths down to 500nm. The submicron OTFTs exhibit negative threshold voltages with an absolute value well below 5V and have subthreshold swings around 0.5V/decade. This demonstrates the possibility to fabricate fully structured and miniaturized OTFTs operating at low voltages and paves the way for a low-cost fabrication of downscaled high performance organic electronic circuits.

Effective Capture Cross-Sections of Traps in High-k Gate Dielectrics

We report an experimental study of captures cross-sections of traps in some ultra-thin high-k gate dielectrics. We focus on a surprising finding that the effective capture cross-sections seemed to be extraordinarily small (between 10e-22 and 10e-19cm2) compared. We arrived at the conclusion that the low values of the effective capture cross-section arise from significant de-trapping, which is not accounted for in the trapping models used in extracting the trap cross-sections. The results of this study point out that it is important to consider the film thickness and leakage current when extracting capture cross-sections in ultra thin gate dielectrics.

Intrinsic Electronically Active Defects in Transition Metal Elemental Oxides

Densities of interfacial and bulk defects in high-κ dielectrics are typically about two orders of magnitude larger than those in Si–SiO2 devices. An asymmetry in electron and hole trapping kinetics, first detected in test capacitor devices with nanocrystalline ZrO2 and HfO2 dielectrics, is a significant potential limitation for Si device operation and reliability in complementary metal oxide semiconductor applications. There are two crucial issues: i) are the electron and hole traps intrinsic defects, or are they associated with processed-introduced impurities?, and ii) what are the local atomic bonding arrangements and electronic state energies of these traps? In this study, thin film nanocrystalline high-κ gate dielectrics, TiO2, ZrO2, and HfO2 (group IVB TM oxides), are investigated spectroscopically to identify the intrinsic electronic structures of valence and conduction band states, as well as those of intrinsic bonding defects. A quantitative/qualitative distinction is made between crystal field and Jahn–Teller (J–T) d-state energy differences in nanocrystralline TM elemental oxides, and noncrystalline TM silicates and Si oxynitrides. It is experimentally shown and theoretically supported that a length scale for nanocrystallite size <2–3 nm i) eliminates J–T d-state term splittings in band edge π-bonded d-states, and ii) represents a transition from the observation of discrete band edge defects to band-tail defects. Additionally, π-state bonding coherence can also be disrupted with similar effects on band edge and defect states in HfO2 films which have been annealed in NH3 at 700 °C, and display Hf–N bonds in N atom K1 edge X-ray absorption spectra.

Electron tunneling spectroscopy study of amorphous films of the gate dielectric candidates LaAlO3 and LaScO3

Electron tunneling spectroscopy (ETS) was used to study amorphous LaAlO3 and LaScO3 thin film gate dielectrics for silicon metal-oxide-semiconductor structure. These gate dielectrics were prepared by molecular-beam deposition on (100) Si substrates. The authors have obtained vibrational modes for amorphous LaAlO3 and LaScO3 thin films from the ETS spectra, which provide information about the chemical bonding in these films and the interface with silicon. Traps and defects in amorphous LaAlO3 thin films are revealed in the ETS spectra, and their physical locations and energy levels are identified.

Influence of oxygen content on the structural and electrical characteristics of thin neodymium oxide gate dielectrics

The structural properties and electrical characteristics of thin Nd2O3 gate oxides were deposited on silicon substrates by reactive rf sputtering. The structural and morphological features of these films were studied, as a function of the growth conditions (three various argon-to-oxygen flow ratios: 20∕5, 15∕10, and 12.5∕12.5 and temperature from 600to800°C), by x-ray diffraction, atomic force microscopy, and x-ray photoelectron spectroscopy. It is found that Nd2O3 dielectrics with a 12.5∕12.5 ratio condition annealed at 700°C exhibit a thinner capacitance equivalent thickness and excellent electrical properties, including the electric breakdown field, the interface trap density, the hysteresis, and frequency dispersion in the capacitance-voltage curves. This condition is suggested to the reduction of the interfacial SiO2 and silicate formation, and the small of surface roughness due to the optimization of oxygen in the metal oxide film.

A Perspective on the Theory of MOSFET Scaling and its Impact

For more than two decades following the publication of the MOSFET scaling theory, CMOS engineers focused their efforts on scaling down the physical size of CMOS transistors. The opportunity for scaled CMOS to break into high-end applications came when the industry worked together to established voltage standards below 5 volt. Two of the limits of CMOS scaling were reached in the early 2000's: high tunneling current through the thin gate insulator and high device off current. Today, device engineers focus primarily on technology innovations for continued device performance improvement from one generation to the next.

Structural and electrical characteristics of thin erbium oxide gate dielectrics

A high-k erbium oxide thin film was grown on silicon substrate by reactive rf sputtering. It is found that the capacitance value of Er2O3 gate dielectric with TaN metal gate annealed at 700°C is higher compared to other annealing temperature and exhibits a lower hysteresis voltage as well as interface trap density in C-V curves. They also show negligible charge trapping under high constant voltage stress. This phenomenon is attributed to a rather well-crystallized Er2O3 and the decrease of the interfacial layer and Er silicate thickness observed by x-ray diffraction and x-ray photoelectron spectroscopy, respectively.

A Three-Dimensional Simulation Study of the Performance of Carbon Nanotube Field-Effect Transistors With Doped Reservoirs and Realistic Geometry

In this work, we simulate the expected device performance and the scaling perspectives of Carbon nanotube Field Effect Transistors (CNT-FETs), with doped source and drain extensions. The simulations are based on the self-consistent solution of the 3D Poisson-Schroedinger equation with open boundary conditions, within the Non-Equilibrium Green's Function formalism, where arbitrary gate geometry and device architecture can be considered. The investigation of short channel effects for different gate configurations and geometry parameters shows that double gate devices offer quasi ideal subthreshold slope and DIBL without extremely thin gate dielectrics. Exploration of devices with parallel CNTs show that On currents per unit width can be significantly larger than the silicon counterpart, while high-frequency performance is very promising.

On the scaling limit of ultrathin SOI MOSFETs

In this paper, a detailed study on the scaling limit of ultrathin silicon-on-insulator (SOI) MOSFETs is presented. Due to the penetration of lateral source/drain fields into standard thick buried oxide, the scale-length theory does not apply to thin SOI MOSFETs. An extensive two-dimensional device simulation shows that for a thin gate insulator, the minimum channel length can be expressed as L/sub min//spl ap/4.5(t/sub Si/+(/spl epsiv//sub Si///spl epsiv//sub I/)t/sub I/), where t/sub Si/ is the silicon thickness, and /spl epsiv//sub I/ and t/sub I/ are the permittivity and thickness of the gate insulator. With t/sub Si/ limited to /spl ges/ 2 nm from quantum mechanical and threshold considerations, a scaling limit of L/sub min/=20 nm is projected for oxides, and L/sub min/=10 nm for high-/spl kappa/ dielectrics. The effect of body doping has also been investigated. It has no significant effect on the scaling limit.

Capacitance–Voltage Measurement Method for Ultrathin Gate Dielectrics Using LC Resonance Circuit

The capacitance-voltage (C-V) measurement method using the LC resonance circuit (LC resonance method) for ultrathin gate dielectrics having large leakage current is demonstrated. In the LC resonance method, only an external inductance and a resistance and a simple equivalent electrical circuit of MOS devices are employed. External inductance can be optimized using the equivalent quality factor. At each gate voltage bias point,parameters of MOS equivalent circuit are determined by fitting the calculation results to the measured impedance-frequency characteristics at the resonance frequency point. Total resistance value of MOS equivalent circuit that is determined from the dc gate current-gate voltage characteristics can be a good help in the fitting sequence. The rms error of calculated and measured impedance-frequency characteristics is used for the fitting verification. The sensitivity of rms error to the variation in MOS capacitance value is discussed to determine the accuracy of the LC resonance method. C-V measurements of both thick (EOT=7.0 nm) and thin (EOT=1.2/spl bsol/ nm) gate dielectrics are demonstrated and the electrical oxide thickness (EOT) values are extracted from the C-V characteristics. Comparison between the LC resonance method and the other C-V measurement methods is also made with respect to C-V measurement results to show the good applicability of the LC resonance method.

A manifestation of the tunneling conductivity of a thin-gate insulator in the generation kinetics of minority carriers in metal-insulator-semiconductor structures

The kinetics of the minority-charge-carrier generation current I(t), in the Al-n+-Si-SiO2-n-Si structures with a tunnel-transparent oxide layer, are found to be anomalous. Under depleting gate potentials (Vg<0), sharp peaks are observed in the I(t) curves, whose descending branches attain a steady-state current level rapidly increasing with |Vg|. The observed features are related to the tunneling conductivity of a thin (100 A) oxide layer and with the impact generation of electron-hole pairs in a space charge region of Si by hot electrons that tunnel into the space charge region. Using this concept, an algorithm of the quantitative description of the experimental data is developed. This algorithm makes it possible to separate the components related to thermal and impact generation and the tunneling current component from the total current I(t). The impact ionization factor (α=1.2±0.2) and the energy of hot electrons in Si space charge region (Eim=4.23 eV) are determined. Dynamic and steady-state current-voltage characteristics for the oxide layer coincide and obey the Fowler-Nordheim law. The position of the current maximum is controlled by external factors that stimulate the generation of non-equilibrium charge carriers; this effect can be used for the development of integrating and threshold sensors.

Excellent frequency dispersion of thin gadolinium oxide high-k gate dielectrics

In this letter, we reported a high-k gadolinium oxide (Gd2O3) gate dielectric formed by reactive rf sputtering. It is found that the Gd2O3 gate dielectric film exhibits excellent electrical properties such as low leakage current density, high breakdown voltage, and almost no hysteresis and frequency dispersion in C-V curves comparable to that of HfO2 film. This indicates that postprocessing treatments can reduce a large amount of interface trap and can passivate a large amount of trapped charge at defect sites.

A Generalized Electrostatic Scale Length for Fully Depleted Surrounding-Gate Metal–Oxide–Semiconductor Field Effect Transistors

On the basis of the continuity of the electric flux and potential at the interface between a Si body and a gate insulator, and of the effective insulator thickness, a generalized electrostatic scale length for two-dimensional (2D) effects in fully depleted surrounding-gate (SG) metal–oxide–semiconductor field effect transistors (MOSFETs) is derived. It is found that for the same equivalent oxide thickness, a gate insulator with a higher dielectric permittivity results in stronger 2D effects caused by an increase in electrostatic scale length. Both a thin gate insulator and a thin Si body are required to realize a small electrostatic scale length to suppress short-channel effects. Compared with conventional planar MOSFETs, high-gate-permittivity SG MOSFETs theoretically can be designed such that its insulator is thicker than its Si body without increasing its electrostatic scale length. With appropriate modification of the effective insulator layer thickness, the model also indicates an increased scale length due to quantum effects.

Positive Bias Temperature Instability in nMOSFETs with ultra-thin Hf-silicate gate dielectrics

Positive bias temperature instability (PBTI) in nMOSFETs with ultra thin HfSiON gate dielectrics has been investigated. We propose that PBTI is due to electron trapping in the high-k dielectrics layer and we present results of measurements performed at different bias condition and temperatures consistent with the proposed model. Extrapolated lifetimes indicate that PBTI in HfSiON gate dielectrics severely impacts the reliability of CMOS devices only in the case of Hf rich-layers.

Low-Voltage, High-Performance Organic Field-Effect Transistors with an Ultra-Thin TiO2 Layer as Gate Insulator

We report on our latest improvements in organic field-effect transistors (OFETs) using ultra-thin anodized gate insulators. Anodization of titanium (Ti) is an extremely cheap and simple technique to obtain high-quality, very thin (∼ 7.5 nm), pinhole-free, and robust gate insulators for OFETs. The anodized insulators have been tested in transistors using pentacene and poly(triarylamine) (PTAA) as active layers. The fabricated devices display low-threshold, normally “off” OFETs with negligible hysteresis, good carrier mobility, high gate capacitance, and exceptionally low inverse subthreshold slope. Device performance is improved via chemical modification of TiO2 with an octadecyltrichlorosilane (OTS) self-assembled monolayer (SAM). As the result of this combination of favorable properties, we have demonstrated OFETs that can be operated with voltages well below 1 V.

RFCV Test Structure Design for a Selected Frequency Range

The problems with the CV characterization on very leaky (thin) nitrided oxide are mainly due to the measurement precision and MOS gate dielectric model accuracy. By doing S-parameter measurement at RF frequency and using simple but reasonably accurate model. we can obtain proper CV curves for very thin nitrided gate dielectrics. Regarding the measurement frequency we propose a systematic method to find a frequency range in which we can select measurement frequencies for all biases to obtain a full CV curve. Moreover, we formulated the first order relationship between the measurement frequency range and the test structure design for CV characterization. With the established formulae, we redesigned the test structures and verified that the formulae can be used as a guideline for the test structure design for RFCV measurements.

Highly Selective Etching of Tantalum Electrode to Thin Gate Dielectrics Using SiCl4-NF3 Gas Mixture Plasma

We have developed a new etching technology for a metal gate electrode with high selectivity to thin gate dielectrics. Dry etching of tantalum (Ta) and tantalum nitride (TaNx) electrodes, not only over thin silicon dioxide (SiO2) but also over thin silicon nitride (Si3N4) gate dielectrics, is achieved by employing an appropriate ratio of silicon tetrachloride (SiCl4) and nitrogen trifluoride (NF3) gas mixture plasma. We confirmed that the high selectivity is due to the formation of a deposition layer caused by plasma polymerization based on SiCl4-NF3 chemistry. In this paper, we also demonstrate excellent characteristics of metal oxide semiconductor field effect transistor (MOSFET) and metal nitride semiconductor field effect transistor (MNSFET) devices using a low-resistivity TaNx/bcc-Ta/TaNx stacked metal gate.

The effect of imaging forces in ultra thin gate insulator on the tunneling current and its oscillations at the region of transition from the direct tunneling to the Fowler–Nordheim tunneling

The influence of imaging forces on the transparency of the tunnel barrier in the Si–SiO 2–Si structures with oxide thickness of a few nanometers was analyzed. It was shown that the substitution of real potential relief with the imaging forces by an effective potential without these forces but with decreased barrier height leads to considerable errors in the transparency. These errors originate from neglecting the real barrier height decrease and the tunneling path reduction with the growth of the applied field. We have calculated the phase of oscillations of the tunneling current in SiO 2 layers as a function of the electric field and of the oxide thickness. The theoretical results are in good agreement with experiments.

Flexible high capacitance gate insulators for organic field effect transistors

We have manufactured flexible field effect transistors with both polymeric and low molecular weight organic semiconductors onto a very thin (6.5 nm) gate insulator with capacitance in excess of 600 nF cm−2. Gate insulators were prepared by anodization of a sputtered aluminium film on a Mylar plastic sheet. Anodization protocols in very dilute acid and in pure water, were explored and results compared.